1 Introduction In recent years, with the development of high-power switching power supplies, the requirements for controllers have become increasingly higher, and the digitalization and intelligentization of switching power supplies will become the future development direction. At present, most high-power switching power supplies in China adopt traditional analog control methods, which are complex and have poor reliability. Therefore, a digital controller with high integration and powerful integrated functions is used to design a switching power supply controller to meet the ever-increasing requirements for programmable control, data communication, and intelligent control of switching power supply output. 2 Digital Controller Design The digital controller designed in this paper uses the TMS320LF2407A chip from the TI 24X series DSP controller as the main controller. The main functional modules include: (1) DSP and programmable logic device CPLD to realize full-bridge phase-shift resonant soft switching drive; (2) bias detection circuit; (3) other functions, such as data acquisition, protection and external interface. The control system structure is shown in Figure 1. 2.1 Generation of Phase-Shift Control Waveform The TMS320LF2407A chip contains two event managers, EVA and EVB. Each event manager includes two general-purpose timers: GPT1 and GPT2, corresponding to event manager EVA and event manager EVB, respectively. The structure of the general-purpose timers is shown in Figure 2. The general-purpose timers are the foundation for PWM waveform generation, and each timer can provide a separate PWM output channel. The process of obtaining a PWM signal with a specified period and pulse width is as follows: First, the general-purpose timer control register TxCON is set to determine the counter's counting mode and clock source; then, the period register TxPR is set according to the required PWM waveform period; next, the compare register TxCMPR is loaded to determine the PWM waveform's duty cycle. Through these settings, a PWM signal with a specified period and pulse width can be obtained. The key to outputting the phase-shift waveform is to synchronize the two general-purpose timers in the same event manager, and to assign a different initial value to the counter of the other general-purpose timer when one timer starts counting from zero. The magnitude of the initial value determines the phase relationship of the PWM waveforms output by the two timers. This paper utilizes the synchronous operation of two general-purpose timers, GPT1 and GPT2, in the event manager EVA to generate phase-shifted waveforms. To avoid the damage caused by the instantaneous shoot-through of the bridge arm due to the current tailing of switching devices, especially IGBT devices, during turn-off, a dead time needs to be added to the control waveform of the switching devices on the same side of the bridge arm. Because PLDs have the ability to be modified online, the design can be modified at any time after the PCB circuit is completed without changing the hardware circuit. Therefore, this paper uses the EPM7000S series CPLD chip from Altera to generate the dead time of the control waveform through programming. As shown in Figure 3. 2.2 Magnetic Deflection Detection Circuit In a full-bridge circuit, a pair of power switches alternately turn on and off in the first half and second half of the working cycle. If their saturation voltage drops are equal and their conduction pulse widths are the same, the circuit is said to be operating in a balanced state. However, if, for some reason, the voltage applied to the intermediate frequency transformer in the two half-cycles is unequal (e.g., a large difference in the saturation voltage drop of the power switch) or the conduction pulse widths of a pair of transistors are unequal (e.g., due to inconsistent storage times, unequal output pulse widths of the control circuit, or asymmetry caused by the feedback loop), the power conversion circuit will operate in an unbalanced state. The transformer's magnetic flux cannot return to the starting point at the end of a cycle, and will therefore increase in one direction, causing its operating region to deviate to one quadrant, leading to core saturation and thus damage to the power switch and inverter failure. This is known as "unidirectional magnetic bias." To avoid transformer saturation, fully utilize the advantages of the digital controller, simplify the main circuit design as much as possible, and increase the transformer utilization rate, the following methods are adopted in this design for magnetic bias detection and control. As shown in Figure 4, the current magnitude of the primary side of the transformer during the positive and negative half-cycles is detected by the current transformer. The detected values ​​HCQ1 and HCQ2 are compared. If the current of a certain half-cycle is larger than a certain value, it is considered that magnetic bias has occurred. This signal is sent to the capture unit function of the TMS320LF2407A to generate a capture interrupt. The interrupt program adjusts the width of the drive pulse of the power switch transistor of the corresponding bridge arm, forcing magnetic recovery of the transformer and preventing transformer saturation. 2.3 Data Sampling and Filtering To ensure signal isolation between the control board and the main circuit of the system, the data sampling circuit uses interfaces with Hall voltage and Hall current sensors to ensure complete isolation between the sampling input circuit signal and the sampling output signal. The TMS320LF2407A chip integrates a 10-bit precision analog-to-digital converter (ADC) module with built-in sample/hold. According to the technical requirements of the system, the precision of the 10-bit ADC can meet the control requirements of voltage resolution and current resolution. Therefore, this paper directly uses the ADC integrated inside the control chip to meet the control precision requirements. In addition, this 10-bit ADC is a high-speed ADC with a minimum conversion time of 500 ns, which also meets the control requirements for the sampling period. To improve the accuracy of ADC digital sampling and reduce the workload of software filtering, a low-pass filter was designed to process voltage and current signals to eliminate high-frequency signal interference and better eliminate interference from lines and space. 2.4 Protection Function During power supply operation, some abnormal states may occur, such as shoot-through in the full-bridge circuit causing a short circuit on the primary bus; short circuit or overcurrent in the secondary load; overheating of the heat sink, etc., which need to be protected in the control. In this design, the function of the DSP power protection pin PDPINT is used to detect abnormal states and handle them in a timely and appropriate manner, so as to ensure the safe and reliable operation of the system. The protection circuit adopts a window comparator circuit to detect the overcurrent signal of the power switch, the output short-circuit signal, and the overheating signal of the heat sink. Set protection thresholds. Once any abnormality occurs, a protection signal can be immediately sent to the DSP power protection pin PDPINT or the external interrupt signal IOPE-2 to notify the control system and take corresponding measures: For short circuits on the primary and secondary sides, an unrecoverable protection mode is adopted, immediately shutting down the PWM drive signal and cutting off the power input to prevent other more serious dangers from occurring; for recoverable protection signals such as heat sink overheating, the PWM output is temporarily shut down and resumed after the state is restored.