Abstract: To address the practical needs of machine vision algorithms, such as large data volume, high-speed transmission, complex calculations, and networking, a real-time video processing system was designed. This system uses AD9200 as the video acquisition A/D converter, TMS320DM642 DSPs as the core processor, applies network technology for image transmission, and uses FPGA to control the output and implement image preprocessing functions. Keywords: Machine Vision, TMS320DM642, Ethernet Abstract: This paper constructs a design of Machine Vision System based on TI Dm642 DSPs. The DM642 device is based on the second-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture (VelociTI.2) developed by Texas Instruments, making these DSPs an excellent choice for digital media applications. This system can sample analog video signals, turn it into digital signals, store it into SDRAM and transmit it based on Ethernet. This system also contains a FPGA. Using FPGA, the system can make some necessary image pretreatment before the video signals gets in DM642. This have a big goodness to take easy DM642's burden, and let DM642 have more time to do the more complex image treatment work. Key Words: Machine Vision;TMS320DM642;Ethernet 1. Introduction Machine vision has a 15-year history of development since its inception. As an application system, its functional characteristics have gradually improved and evolved along with the development of industrial automation. Currently, the application of vision systems internationally is booming, with a market size of $4.6 billion in 1998. Abroad, the widespread application of machine vision is mainly reflected in the semiconductor and electronics industries, with approximately 40%-50% concentrated in the semiconductor sector, specifically in PCB printed circuits. Major machine vision companies include Krones AG of Germany and Industrial Power Machinery Inc. of the United States. In China, however, industrial vision systems are still in the conceptual introduction stage, resulting in limited applications in the aforementioned industries. Even when they are used, they are mostly low-end applications. Most domestic companies primarily act as agents for foreign products, with relatively little independent research and development. This leads to relatively high prices for these products in China, causing many factories to abandon the idea of ​​using machine vision after weighing the pros and cons. However, with the improvement of my country's supporting infrastructure and the accumulation of technology and capital, the demand for industrial automation and intelligentization using image and machine vision technologies has begun to emerge widely across various industries. Simultaneously, due to the decline in the price of video acquisition system hardware, domestic universities and research institutes have actively explored and boldly experimented in the field of image and machine vision technology in the past two years, gradually beginning to apply it in industrial settings. Furthermore, leading companies in various industries, having solved the problem of production automation, have begun to turn their attention to visual measurement automation. These applications are mostly concentrated in areas such as pharmaceutical testing and packaging, and printing color detection. Truly high-end applications are still rare; therefore, the application space in the aforementioned related industries is still relatively large. Embedded systems and networking are two trends in the development of machine vision systems: 1) Embedded systems enable tighter integration of data acquisition, automatic control, and image detection; additionally, machine vision systems based on embedded systems have extremely low power consumption. 2) Networking is a development trend of embedded systems, and its application in industrial automation is becoming increasingly widespread. The combination of machine vision with advanced technologies such as network communication is changing the face of industrial automated production. Currently, the integration of machine vision with advanced technologies such as motion control and network communication is changing the face of industrial automation production. Companies with technical backgrounds in motion control, machine vision, and network communication will undoubtedly be at the forefront. 2. System Hardware Design This design uses beer bottle detection as its design background. Combining these two major development trends in machine vision, an embedded system based on the TI TMS320DM642 was developed, and Ethernet technology was applied for image transmission. Design module schematic diagram: [align=center] Figure 1. Hardware Composition[/align] 2.1 Video Acquisition Module The analog video signal adopts a non-standard format. The camera operates in an external trigger mode, with the trigger signal provided by the FPGA. Each trigger transmits a single frame signal. The video signal entering the circuit board has an amplitude of 1V. It is first amplified and clamped by the video operational amplifier EL4089, increasing the amplitude to 2V. Then the signal is split into two paths: one path is sent to the ISL59885 video synchronization separator chip to generate horizontal and vertical synchronization signals, and the other path is converted from analog to digital by the AD9200. The video signal is decoded to obtain line synchronization, field synchronization, and 8-bit luminance signals, which are then sent to the FPGA module. 2.2 FPGA Module: Altera's EP1K100 series is a cost-effective programmable logic device with 100,000 equivalent system gates, a core voltage of 2.5V, port voltage compatibility of 5V and 3.3V, and an operating frequency up to 250MHz, meeting the multi-voltage, high-frequency operation requirements of this card. This part is mainly responsible for the logic control and timing adjustment of the entire board. The FPGA receives the video's line and field synchronization and luminance signals and performs image preprocessing within the FPGA, including binarization, Sobel edge segmentation, and median filtering. The processed luminance signal is then sent to the DM642's video port. Because the ISL59885 generates a separate line synchronization signal for every two lines, the FPGA must add a new line synchronization signal between every two line synchronization signals for correct acquisition, sending it to the DM642's video port. In addition, the FPGA is also responsible for the sampling frequency and clamping signal generation of the video acquisition section, the generation of parallel IO control signals, and the selection of the RS-232 and RS-442 communication protocols for the serial interface section. 2.3 DM642 Module and Storage Module 2.3.1 TMS320DM642 Module: The DM642 is a newly launched chip from TI for video and image processing. It uses the core of the TMS320C64X series DSPs and integrates some peripheral devices for video and image processing, such as three configurable video ports, a 10/100Mbps Ethernet MAC, a multi-channel serial audio interface (McASP), and a 66MHz 32-bit PCI bus. The TMS320DM642 uses TI's second-generation high-performance Very Long Instruction Word (VLTI) structure VelociT1.2TM, which can execute two 16*16-bit multiplications or four 8*8-bit multiplications in each clock cycle. The TMS320DM642 contains six arithmetic logic units (ALUs), capable of performing two 16-bit or four 8-bit addition, subtraction, comparison, and shift operations per clock cycle. At a clock frequency of 600MHz, the DM642 can perform 2.4 billion 16-bit multiply-accumulate operations or 4.8 billion 8-bit multiply-accumulate operations per second. This powerful computing capability enables the DM642 to perform real-time multi-video and image processing. This design utilizes the video port for image acquisition and an Ethernet interface for image transmission. The video port supports input and output of various video data formats, including BT.656, HDTV Y/C, and MPEG-2 Transport stream input. This design employs progressive scan and acquires only luminance data, with the video port operating in YcbCr 4:2:2 mode. The video port is integrated with the DM642's EDMA; an EDMA synchronization event is initiated after each line of image data is acquired, temporarily transferring the data from the receive FIFO to the SDRAM. After each line of image data acquisition, the EDMA parameters are automatically reconfigured using the EDMA link. The entire image acquisition process consumes very little CPU time, allowing the CPU to focus on subsequent image processing. 2.3.2 The memory module expands to include both SDRAM and FLASH memory. 1) SDRAM memory: A 64-bit SDRAM bus is connected to the CE0 space. Two 48LCHM3282 chips are selected to form the SDRAM. This 32MB SDRAM space is used to store image data and intermediate image processing results. The bus is controlled by an external PLL driver and operates at an optimal speed of 133MHz. SDRAM refresh is automatically controlled by a TMS320DM642. 2) FLASH memory: This system expands to include 1MB of FLASH memory, mapped to the lower bits of the CE1 space. 1MB*8 MBM29DL800 chips are selected for the FLASH memory. The FLASH memory is mainly used for storing DSP programs. The CE1 space is configured as 8 bits with an asynchronous interface, and the FLASH memory is also 8 bits. The default address after reset is 000, and a 1KB data is automatically booted upon power-up. 2.4 The EMAC interface on the DM642 Ethernet module provides an effective interface between the DSP processing core and the network. It supports 10Base-T and 100Base-TX, and can operate at speeds of 10 Mbits/second and 100 Mbits/second for full-duplex or half-duplex transmission. It also provides hardware flow control and QoS support. The DM642's EMAC interface supports the data link layer of computer network protocols and supports the standard MII interface (Media Independent Interface) for connection to physical layer devices. The physical layer device uses Broadcom's BCM5221, plus a Pulse 1:1 isolation transformer H1102. Network image and control information transmission uses the connectionless UDP protocol, capable of transmitting 20 frames per second for 480*480 8-bit grayscale images. 2.5 The IO module and serial interface module: The IO interface is controlled by the FPGA and used to send control signals to the mechanical and automatic control parts. There are two parallel IO interfaces: one driven by an LV162245, and the other isolated via an optocoupler. The serial interface uses TI's TL16C752B UART, which is pin compatible with ST16C550 UART and has larger transmit and receive FIFO buffers (64 bytes each for transmit and receive), supporting hardware and software flow control. Level conversion uses MAXIM's MAX3160, supporting multiple transmission protocols such as RS-232, RS-485, and RS-422. 3. FPGA Implementation of Image Preprocessing Algorithm Taking FPGA implementation of 3x3 Sobel edge detection as an example, this section introduces the method of FPGA-based image preprocessing. First, a 3x3 image frame should be extracted from the video signal. Three FIFOs, each the same size as a row of pixels, are used and connected serially. The first three rows of the video signal fill the three FIFOs. Afterward, for each incoming pixel, while writing to the FIFO, the brightness value of one pixel is read from each FIFO and placed into the three shift registers. Thus, a 3x3 rectangle is obtained after three pixels. As the video signal continues to flow, the rectangle will traverse the entire image area. After that, the extracted pixels can be processed using various algorithms. The following is the 3*3 Sobel operator described in Verilog language: wire[10:0] temp1,temp2,temp3,temp4; wire[7:0] sobel1,sobel2,sobel3,sobel4; wire[7:0] dataout; assign temp1 = temp[1] + temp[2] + temp[3]; assign temp2 = temp[7] + temp[8] + temp[9]; assign temp3 = temp[1] + temp[4] + temp[7]; assign temp4 = temp[3] + temp[6] + temp[9]; assign sobel1 = (temp1>temp2)? (temp1-temp2):0; assign sobel2 = (temp3>temp4)? (temp3-temp4):0; assign sobel3 = (sobel1>8'd 255) ? 8'd255 : sobel1; assign sobel4 = (sobel2>8'd 255) ? 8'd255 : sobel2; assign dataout[7:0] = ((sobel3 > sobel4)?sobel3[7:0]:sobel4[7:0]); This design takes into account the overflow of data calculation or the negative value of the result, and the edge detection effect is good. 4. Conclusion This design builds a hardware platform for the image processing part of the machine vision system, combining the two major trends in the development of machine vision systems: embedded systems and network technology. Based on the TMS320CDM642 DSP chip recently launched by Texas Instruments, the combination of video acquisition and network technology is realized by utilizing the Video Port and Ethernet Media Access Controller provided on the TMS320DM642 chip. Using in-circuit programmable technology, the necessary image preprocessing algorithms are implemented in the FPGA, reducing the burden on the TMS320DM642 and laying a good foundation for subsequent real-time image detection. This design achieves smooth transmission of 480*480 grayscale images at 25 frames/s via Ethernet. The following is the effect of the Sobel edge extraction algorithm implemented by FPGA: [align=center] Figure 3. Original image and image after Sobel edge extraction[/align] Innovative viewpoint: This paper combines machine vision and network technology, uses the newly launched 6000 series DSPs TMS320DM642 of TI as the core, and applies ALTERA's FPGA to implement image preprocessing, reducing the burden of DSPs. Network technology is applied to realize image transmission. References: [1] Xu Zhijun, Xu Guanghui. Development and application of CPLD/FPGA. Beijing: Electronic Industry Press, 2002 [2] TI. TMS320DM642 Data Sheet. [3] TI. TMS320C6000 DSP EMAC/MDIO Module Reference Guide. [4] TI. TMS320C64x DSPVideo Port/VCXO Interpolated Control (VIC) Port Reference Guide. [5] Samir Palnitkar. Verilog HDL Digital Design and Synthesis (Second Edition). Beijing: Electronic Industry Press, 2004 [6] Li Fanghui, Wang Fei, He Peikun. TMS320C6000 Series DSPs Principles and Applications (Second Edition). Beijing: Electronic Industry Press, 2003 [7] Pan Jijun, Design of C6000DSK Video Processing System, Microcomputer Information, 2006, No. 4-2, P135-136 [8] Wang Xiwei, Optimization Strategy of Video Coding Cache Based on DM642, Microcomputer Information, 2005, No. 9-2