[align=left] 1 Introduction EEPROM is a type of memory with power-off memory function. Its contents can be rewritten like ordinary RAM, and it can automatically erase and replace the contents during rewriting. Unlike EPROM, it does not require ultraviolet light erasure; it only requires electricity to erase and rewrite the contents stored inside. EEPROM usually has an internal programming power supply. Since it only requires a single external +5V power supply, it is very convenient to use. Compared with serial chips, the circuit interface and programming design of parallel EEPROM are much simpler, so it is still very convenient to use EEPROM memory when the requirements for board area are not very strict. [b]2 Reasons for Data Loss in Parallel EEPROM[/b] Parallel EEPROM usually adopts the bus expansion interface method. Figure 1 shows the interface circuit based on AT28C256, where the chip select signal generated by address decoding is the read and write signal of the microcontroller. [/align][img=224,250]http://zszl.cepee.com/cepee_kjlw_pic/files/wx/gydzyqj/2002-2/26-1.jpg[/img] When programming, only one MOVX instruction is needed to complete the read and write operations of the EEP-ROM memory, which is very convenient. However, parallel EEPROMs are often subject to interference in industrial settings, which can cause changes in the data stored inside, resulting in data damage or loss. According to analysis, data loss of EEPROM memory mainly occurs when the system is powered on, powered off, or reset. It is mainly manifested in the following two situations: (1) When the CPU in the entire data storage system is released from the reset signal, it will generally be delayed for hundreds of μs. Therefore, during this period, the read signal, write signal, address signal, and data signal may change randomly, which may cause erroneous write operations to the memory and change the data in it. (2) During the slow rise and fall of the power supply, when the CPU is in a critical working state, its read and write timing may become disordered, thereby changing the data in the memory. [b]3 Introduction to AT28C Series EEPROM[/b] Figure 2 shows the logic block diagram of the AT28C series parallel EEPROM memory of ATMEL. The main products in this series include AT28C64 (8K×8), AT28C256 (32K×8), AT28C010 (128K×8), AT28C040 (512K×8), etc., and their structures are basically the same. Compared to ordinary 28-series EEPROMs, the AT28C series EEPROMs have the following characteristics: ● 64, 128, or 256 bytes of identifier bytes (varies depending on the model); ● Fast read speed, with a read time range of 120ns to 150ns; ● Two write modes: byte and page. In page write mode, the EEPROM's internal timer controls the timing sequence to write one page of data within one internal programming cycle, with a page capacity of 64, 128, or 256 bytes (depending on the model); ● Data protection features and excellent anti-interference capabilities. [img=286,165]http://zszl.cepee.com/cepee_kjlw_pic/files/wx/gydzyqj/2002-2/27-2.jpg[/img] Among these features, the most attractive is undoubtedly the comprehensive data protection function. [b]4 Data Protection Measures for the AT28C Series[/b] The AT28C series EEPROM generally employs two types of measures: hardware data protection and software data protection (SDP). 4.1 Hardware Data Protection The hardware data protection measures for the AT28C series EEPROM are as follows: The first measure is to monitor Vcc. When Vcc is below 3.8V, writing to the EEPROM is prohibited. The second measure is to use a power-on delay, that is, when the system is powered on, after Vcc rises to 3.8V, a delay of 5ms is allowed before data writing is permitted. The third measure is write prohibition, that is, when any of the three conditions of low level, high level, or high level occur, data writing is prohibited. The last measure is to use noise filtering so that pulses narrower than 15ns on the signal line cannot trigger write operations. 4.2 Software Data Protection The software-controlled data protection function can be enabled or disabled by user programming. It is set to disabled at the factory. [img=189,154]http://zszl.cepee.com/cepee_kjlw_pic/files/wx/gydzyqj/2002-2/27-1.jpg[/img][img=217,212]http://zszl.cepee.com/cepee_kjlw_pic/files/wx/gydzyqj/2002-2/27-6.jpg[/img] The chip can enter SDP state by executing a sequence of three specific write instructions. Once the chip is in SDP state, this sequence of write instructions should be executed first to enable writing to the chip, followed by byte or page write operations, and then the EEPROM should automatically enter SDP state again. The enable algorithm for the AT28C256 is shown in Figure 3. The C51 program that stores a byte array `mydata` of length N (N < 64) in RAM into a contiguous memory space starting at address `address` in the AT28C256 is as follows: [img=258,108]http://zszl.cepee.com/cepee_kjlw_pic/files/wx/gydzyqj/2002-2/27-7.jpg[/img] The address and data values ​​of the three write instruction sequences will differ for different models. For the AT28C64, the three address values ​​are 1555, 0AAA, and 1555, while the three data values ​​are the same. The algorithm for exiting SDP state (as in the AT28C256) is shown in Figure 4. The address and data values ​​will also differ for different models. It should be noted that the three write instruction sequences mentioned here are only used for the logical judgment required by the SDP inside the EEPROM and will not change the contents of these three addresses in the EEPROM. **5. Conclusion** The author previously used an MP-100 programmer to rewrite an AT28C256 chip with SDP functionality, but failed to change the content of any single byte. In several instruments developed, data loss has never occurred after using this technique to expand the AT28C series EEPROM. Practice has proven that the data protection function of the AT28C series EEPROM is very effective, especially its software data protection function. Due to its excellent anti-interference capability, it is highly recommended for use.