With the rapid development of the national economy, digital image processing is widely used in various fields of social life. The DM642, as a high-performance video processing chip, is widely used in many areas of video processing. However, the I2C application of the DM642 is prone to I2C and VP deadlocks, as well as problems with the incorrect setting of the slave address of the SAA7115. This article mainly introduces the correct initialization of the I2C module in a video acquisition and processing system based on the DM642, and the correct read/write program for the registers of the video decoding chip SAA7115 via the I2C bus. 1 Initialization of the I2C Bus Controller To correctly use the built-in I2C module of the DM642, proper initialization is required first. 1.1 Unlocking the I2C Module in the DM642 In the I2C application of the DM642, it is easy to encounter the problem of not being able to use the initialized I2C module. The reason is that the I2C module has not been unlocked and enabled first. As can be seen in the DM642 datasheet, the I2C module is in a locked and disabled state after reset. In other words, the I2CoEN bit in the hardware configuration register PERCFG is 0, so the I2C module must be enabled before configuring the I2C module control register. However, if you want to modify the contents of PERCFG, you must first write 0x10C0010C to PCFGLOCK to unlock PERCFG. The following is a guide to enabling the I2C module: [img=580,184]http://cms.cn50hz.com/files/RemoteFiles/20081225/201303001.jpg[/img] 1.2 I2C Module Clock Selection After enabling the I2C module, its control register can be initialized. The CPU clock frequency is 600 MHz, and the I2C module specifies that the module clock frequency must be selected from 7 to 12 MHz, so the I2C module clock frequency is set to 10 MHz. From the calculation formula in Figure 1, we can obtain: IPSC is OEh. Since both the DM642 and SAA7115 support the 400 kbps fast mode of the I2C bus, according to the IPSC value, as shown in Figure 1, d=5. Therefore, we can set: ICCL=7, ICCH=8. [img=580,402]http://cms.cn50hz.com/files/RemoteFiles/20081225/201303002.jpg[/img] 1.3 Common Problems Encountered When Setting the Slave Address It is important to note that in the I2C application of the DM642, problems frequently arise regarding the inability to correctly read/write to the slave device. This is because the DM642's slave address register settings differ from those of other chips. In the standard I2C protocol, the 7-bit address format of the device requires both the address and read/write direction bits to be sent to the slave address register. However, in the I2C application of DM642, only the 7-bit device address needs to be sent to the slave address register, and the read/write direction bit is automatically generated by DM642. For example, the standard I2C write slave address of SAA7115 is 40H, as shown in Figure 2. [img=545,211]http://cms.cn50hz.com/files/RemoteFiles/20081225/201303003.jpg[/img] The standard I2C protocol includes 21H of address information and the last bit (read/write direction bit). DM642 only needs to send 21H to the slave address register. If 40H is sent, it will cause a read/write error. 2 I2C Read/Write Software Design 2.1 Configuration Mode Register I2CMDR After each sub-address operation of SAA7115, its address pointer will automatically increment, but the sub-addresses of its configurable registers are not continuously distributed. Therefore, the I2C working mode register (I2CMDR) is configured to counting mode. Each execution of I2C_write() transmits data only once, and the SAA7115 is initialized by calling I2C_write() multiple times. First, 4620H is written to I2CMDR. When reading the SAA7115 registers, it is set to non-repeating master receive mode, and 4420H is written to I2CMDR. 2.2 Configuring the Slave Address Register I2CDXR The DM642 configures the SAA7115 through addressing. When the DM642 writes data to the decoding chip SAA7115, it sends an addressing instruction through the I2C bus, writing the right-shifted 7-bit slave address of the SAA7115 into the I2CDXR register. The following is the initialization program: [img=580,377]http://cms.cn50hz.com/files/RemoteFiles/20081225/201303004.jpg[/img] 2.3 I2C Read/Write Program Design for SAA7115 In summary, Figures 3 and 4 show the flow chart of the DM642 read/write program for SAA7115. [img=580,754]http://cms.cn50hz.com/files/RemoteFiles/20081225/201303005.jpg[/img] Conclusion The program designed in this paper has been proven through operation that, by configuring the I2C bus control registers, the DM642 correctly reads/writes to the SAA7115 video decoding chip, completing the settings of internal registers such as video signal input format, video signal channel selection, video data output format, synchronization signal insertion position, brightness, chroma and contrast settings, synchronization signal input switch, and video acquisition quantization start and stop.