Introduction
Traditional motion control cards mostly use microcontrollers as microprocessors and control servo motors through large-scale integrated circuits. Due to their complex structure, they suffer from drawbacks such as slow high-frequency response and low control precision during operation.
This paper proposes a motion control card with FPGA (field-programmable blegate array) and interface chip as the core hardware. The internal hardware interface and algorithms are implemented through FPGA programming. This not only overcomes the shortcomings of traditional motion control, but also greatly improves flexibility and portability.
Hardware composition and design
1. The motion control card described in this paper is an interface card, using an Altera FPGA (model number) as the programming logic device to implement all hardware algorithms and feedback signal detection. A closed-loop control method using pulse plus direction is employed to control the motor. The entire motion control card system can be described by Figure 1.
2. When designing the hardware circuit of the motion control card, the synchronous timing design principle is strictly followed. The core circuit is implemented using D flip-flops, and the main signals of the circuit are generated by the rising edge of the clock. This can effectively avoid glitches, and there are no glitches in the simulation after layout and in the sampling of the actual working signals by a high-speed logic analyzer. In the control of the high-speed changing frequency division multiple data stream, in order to ensure the real-time performance of the frequency division output of the entire system, the "ping-pong operation" technique shown in Figure 2 is adopted. In the odd (2n+1) buffer cycles, the input data stream is buffered to and retrieved from RAMII to the arithmetic module. In the even (2n) buffer cycle, the data stream is buffered to RAMII, and the data in RAMII is selected by the "data output selection unit" and sent to the final frequency division and counting arithmetic module for calculation and output. This cycle repeats continuously. This pipeline algorithm can achieve seamless data buffering and processing.
The motion control card described in this paper involves four modules: a bus controller, a frequency divider, a timer, and feedback control. Its schematic diagram is shown in Figure 3. The bus controller handles the arbitration logic, address decoding, and data flow control of the PC19054 local bus, ensuring that data on the PCI data bus is correctly decoded and processed by each sub-control module. The timer implements hardware timing. The computer inputs a time value and a control word indicating the start of timing to the motion control card through the driver program. The motion control card starts timing, and upon completion, a hardware interrupt (mode 0) is generated, triggering the interrupt service routine to accurately position the motor's rotation angle. User code can also be used as interrupt handling subroutines to implement timing switching or computation functions. The frequency divider divides the operating frequency (40 MHz) to obtain the pulse frequency controlling the motor speed. The feedback control module implements motor output compensation and status monitoring functions, allowing for error correction by reading errors, thereby improving system control accuracy. These modules are described within the FPGA using a combination of schematic diagrams and VHDL, making the logic hierarchy clearer and more readable.
Algorithm design .
1. Real-time Frequency Division Algorithm: The motion control card outputs different pulse frequencies to control the motor speed. Therefore, the response speed of the pulse frequency determines the control accuracy of the entire motor. This necessitates that we fully consider the real-time performance of the frequency division algorithm when designing the algorithm. This paper proposes a frequency division algorithm based on a counter that increments by two, which can effectively solve this problem. The specific flowchart of the algorithm is shown in Figure 4. The phase-locked loop output clock is taken as the global clock of the design, and two single-port RAMs are used to cross-refresh the frequency division factor. The counter increments by two counts the rising edge of the input clock and compares its count value. If the count value is greater than or equal to twice the frequency division factor, the output is 1', otherwise it is 0'. This implements the frequency divider function. The output of the frequency divider is the pulse (clkout) that the motion control card uses to control the motor speed.
2. Closed-Loop Control Algorithm The entire motion control card employs a pulse-plus-direction control method to control the motor's speed and direction. To ensure motor control accuracy, while the motion control card outputs pulses to the motor driver, it simultaneously reads feedback pulses and direction signals from the encoder. Thus, by designing two counters to simultaneously count the output and feedback pulses, and by judging and differing the count values of the two counters, and then performing cyclic interpolation based on the calculated difference, closed-loop control of the motor can be achieved.
Debugging and result simulation .
1. System Debugging This card uses Signal Tap II, which comes with the Quartus II software, for simulation debugging. Signal Tap II is an embedded logic analyzer based on a logic analysis core. During use, debuggers do not need external specialized instruments; they can capture all signals and nodes within the FPGA device to analyze and diagnose system faults. The entire debugging process is very intuitive and convenient. Signal Tap II acquires data at the rising edge of the acquisition clock. Inappropriate acquisition clock settings can sometimes result in data that does not accurately reflect the desired design state. Altera recommends using a global clock. This paper presents a scenario using the global clock gclk as the acquisition clock, level 1 triggering, and RESULT = ELD({HOLD, 1, ) as the trigger logic. The analysis results are shown in Figure 5. It is worth noting that after debugging, the files should be removed from the design directory to avoid wasting resources.
2. Debugging Results and Error Analysis From the debugging results in Figure 5, the entire control of the motion control card follows the bus arbitration logic. PCI and FPGA data exchange occurs when READY = 0, and data on the bus is valid when READY = 0. Changing the value of the frequency divider register immediately changes the frequency divider output frequency, meeting the design goals. The system detects and judges external signals such as motor travel, alarm, zero position, and servo. It also detects and counts the feedback clock. Since both PCI and data exchange occur on the rising edge of the system clock, there will inevitably be a delay error of less than one clock cycle during data exchange.
Conclusion
The motion control card described in this article has the following features: The data input/output ports use optical isolation technology to avoid unnecessary interference; the FPGA uses an independent 40MHz clock and phase-locked loop design to ensure system clock stability; a divide-by-two algorithm is used to improve the real-time performance of the divided output; the FPGA serves as the core processing chip, reducing hardware costs, simplifying hardware design, and improving real-time performance. Through state detection and feedback modules, motor state detection and error correction are achieved; an interrupt timing module is designed to achieve motor angle control.
References:
Li Guishan, Chen Jinpeng. PCI Local Bus and Its Applications [M]. Xi'an: Xi'an University of Electronic Science and Technology Press, 2003: 8.16.
Zhou Zhiming. Stepper motor control system based on motion control card [J]. Coal Mine Machinery, 95-97.
Wu Jihua, Wang Cheng. Alte mF P GA/CPLD Design [M]. Beijing: Posts & Telecom Press, 2005: 17.21. PCI 9054 databook [EB]. http://www.com/dts/download.asp?f=/PCI 9000/9054/databook/-21.pdf, 2000.
Tong Peng, Wu Xinjian. In-depth study on several issues in the design of PCI 9054 chip interface. Electronic Technology Application, 2005(10): 64-66.
Hu Gang, Shi Yawei. Interrupt handling technology of PCI bus [J]. Computer Automatic Measurement and Control, 2001, 9(6): 55-56.
Ren Aifeng, Chu Xiuqin. Embedded System Design Based on FPGA [M]. Xi'an: Xi'an University of Electronic Science and Technology Press, 2005: 333-354.
Guo Jiajia, Hu Xiaojing. Debugging FPGA using Signal Tapl I logic analyzer [J]. Today's Electronics, 2005 (5): 45-47.
Click to download materials: Design and Implementation of a Motion Control Card Based on FPGA (Edited by He Shiping)
