CAN (Controller Area Network) is one of the most widely used fieldbuses internationally. Originally introduced by Bosch in Germany, the CAN communication protocol is a data communication protocol used between measurement and actuation components within automobiles. As a technologically advanced, highly reliable, feature-rich, and cost-effective remote network communication control method, the CAN bus has been widely applied in various automated control systems. For example, in automotive electronics, automatic control, intelligent buildings, electronic systems, and security monitoring, the CAN bus has unparalleled advantages. This design presents a CAN bus node scheme. It uses the PLC2294, a multi-channel CAN bus controller, as the main controller, making the node small in size, low in power consumption, and with good anti-interference capabilities, thus making it particularly suitable for automotive, industrial control, medical systems, and fault-tolerant maintenance buses. 1 Hardware Design 1.1 Features of the LPC2294 The ARM7 series, with its ARM7TDMI core, is a widely used 32-bit embedded microprocessor and a widely used embedded RISC processor. This series of chips is small in size, low in power consumption, and low in cost, combining high performance with flexibility. It features numerous registers and provides an expanded, enhanced fixed-length 16/32-bit dual instruction set. Using 16-bit Thumb instructions can save up to 35% of space. Furthermore, it implements waterline operation, provides embedded ICE2RT logic, supports on-chip breakpoints and debug points, and offers an advanced software development and debugging environment. The LPC2294 selected in this design is a powerful, ultra-low-power 32-bit microcontroller with an ARM7TDMI core, recently released by PHILIPS. It features a 144-pin package, two 32-bit timers, eight 10-bit ADCs, four CAN channels and a PWM channel, and up to nine external interrupts. Internally, it embeds 256KB of high-speed Flash memory and 16KB of static RAM, and includes 76 (using external memory) to 112 (per chip) GPIO ports. Such abundant on-chip resources fully meet the needs of general industrial control while reducing the complexity of system hardware design. In addition, the LPC2294 supports JTAG real-time emulation and tracing, a 128-bit wide memory interface, and a unique acceleration architecture, enabling 32-bit code to run at operating frequencies up to 60MHz. The LPC2294 integrates four CAN controllers: compliant with CAN specification CAN2.0B, ISO 11989-1 standards; bus data baud rates up to 1Mbps; access to 32-bit registers and RAM; a global acceptance filter that recognizes almost all 11-bit and 29-bit Rx identifiers on the bus; and a FullCAN-style automatic reception function for selected standard identifiers. As the core component of this design, the LPC2294 not only acts as the main controller but also as a node controller in the CAN network, enabling data transmission and exchange with other nodes in the network. 1.2 CAN Node Hardware Circuit Composition The CAN node hardware circuit consists of an ARM microcontroller LPC2294, a CAN bus transceiver TJA1050T, a high-speed optocoupler 6N137, and a power isolation module B0505S. The main control chip, LPC2294, has a crystal oscillator frequency range of 1–30MHz. This design selects a 20MHz crystal oscillator frequency, and the CPU clock frequency can be increased by setting the internal VPB divider. An internal 256KB high-speed Flash memory is used for code and data storage. The Flash memory can be programmed in-system (ISP) or in-application (IAP) via the built-in serial JTAG interface. These interface circuits can be reserved in the design for easy debugging and system upgrades. The LPC2294 uses a dual power supply. The CPU power supply voltage range is 1.65–1.95V (1.8V±8.3%), and the I/O power supply voltage range is 3.0–3.6V (3.3V±10%). The TJA1050T transceiver is the interface between the CAN protocol controller and the physical bus, and it is fully compatible with the "ISO 11898" standard. The ideal combination of CANH and CANL can minimize electromagnetic radiation. In addition, when the TJA1050T is not powered on, the bus exhibits passive characteristics, which makes the TJA1050T significantly superior in performance to previous CAN bus transceivers. The TJA1050T has two operating modes: high-speed mode and silent mode (controlled by pin "S"). In high-speed mode, the bus output signal has a fixed slope and switches as quickly as possible. High-speed mode is suitable for maximum bit speed and maximum bus length, and its transceiver cycle delay is minimized. In silent mode, the transmitter is disabled. It ignores the TxD input signal. Silent mode prevents the CAN controller from blocking network communication when it is not under control. 1.3 Hardware Anti-interference Design In the application scenarios of this design, there are many devices that generate electromagnetic signals, including VHF devices, audio devices, power supplies, etc., so anti-interference devices are particularly important. The following measures were mainly taken: (1) In order to further improve the anti-interference capability of the CAN bus nodes and ensure that each node is electrically isolated and independent, the TX0 and RX0 of LPC2294 are connected to the RXD of TJA1050T through high-speed optocoupler 6N137. However, it should be noted that the two power supplies used in the optocoupler circuit must be completely isolated, otherwise the use of optocouplers will lose its meaning. The complete isolation of the power supply is achieved by using the low-power power isolation module B0505S. Although the circuit is more complex, it improves the stability and safety of the nodes. (2) Two 120Ω resistors are added to both ends of the CAN bus. These two resistors play a very important role in the matching of bus impedance. Removing them will greatly reduce the anti-interference capability and reliability of data communication, and may even prevent communication. (3) Two 30pF small capacitors are connected in parallel between CANH and CANL and ground, which can filter out high-frequency interference on the bus and have a certain ability to prevent electromagnetic radiation; a 5.6V TVS diode is connected in parallel between the two CAN bus access terminals, which can play a certain overvoltage protection role through the short circuit of the TVS diode when voltage interference enters the CAN bus. (4) In order to reduce the interference to the nodes in the field, shielded twisted pair cables are used, and according to actual usage experience, the shielding layer of the shielded cable does not need to be grounded. 2 Software Design The software debugging environment adopts ARM's ARM core processor integrated development tool ADSv1.2. ADSv1.2 integrates assembler, C, C++ compiler and debugger, with high compilation efficiency, providing powerful system libraries, and supporting software debugging, JTAG simulation debugging and hardware debugging. This design uses JTAG simulation debugging. For general 32-bit ARM application systems, the runtime environment must be initialized before running the main program, that is, the startup code for the ARM chip must be written. The startup code includes exception vector table, stack initialization, memory system initialization and target board initialization, etc., and is generally written in assembly language. The key to this design is writing the CAN driver. The main program only needs to call the interface provided by the driver to realize data reception and transmission. The driver consists of four parts: CAN controller initialization, data reception, data transmission, and bus exception handling. 2.1 CAN Controller Initialization The initialization of the CAN controller includes: hardware enable, software reset, device alarm limits, device bus baud rate, device interrupt mode, device acceptance filter mode, device operating mode, and starting CAN, etc. The initialization procedure is as follows: HwEnCAN(CanEum); // Hardware enable, CanNum=0～3, refers to the four-channel CAN controller SoftRstCAN(CanNum); // Software reset register CANEWL(CanNum).Bits.EWL_BIT=USE_EWL_LAN[CanNum]; // Set error warning limits CANBTR(CanNum).Word=USE_BTR_CAN[CanNum]; // Initialize baud rate VICDefVectAddr=(UINT32)CANIntPrg; // Initialize interrupts as non-vectored interrupts VICIntEnable 1=(1<<19)|(1<<(20+CanNum))|(1<<26+CanNum)); CANIER(CanNum).Word=USE_INT_CAL[CanNum]; CANAFMR.Bits.Accbp_bit=1; // Configure acceptance filter (bypass state, i.e., disable acceptance filter) CANMOD(CanNum).Bits.TPM_BIT = USE_TPM_CAN[CanNum]; // Initialize working mode CANMOD(CanNum).Bits.LOM_BIT = USE_MOD_CAN[CanNum]; SoftEnCAN(CanNum); // Start CAN The connection between the LPC2294's on-chip peripherals and pins is controlled by the pin connection module. Hardware enable of the CAN controller is achieved by controlling the multiplexer through software device GPIO registers, connecting specific pins to the CAN controller. A software reset must be performed before accessing each CAN register, as some CAN registers must be read and written in a soft-reset state. It is worth noting that the LPC2294 provides a global receive identifier lookup function for all CAN controllers. The 2K RAM can hold 1024 standard identifiers, 512 extended identifiers, or a mixture of both types. Through software processing, tables of 1 to 5 identifiers can be set up in this RAM. Compared to the standalone CAN controller SJA1000, it can more easily filter arbitrarily complex IDs, meeting complex ID receive filtering requirements. This undoubtedly greatly reduces the complexity of system software design and the burden on runtime. To set the acceptance filter's operating mode, the first step is to create a LUT table, specify the starting address of each table, and initialize the table with the actual ID address. Finally, set the acceptance filter mode register. If the node does not actively send data, it can choose to enter sleep mode when the bus is inactive. 2.2 Data Transmission After packaging the data to be transmitted into a frame format conforming to the CAN protocol, it can be written to the transmit buffer and automatically transmitted. Its status must be checked before writing to the transmit buffer. Each CAN controller in the LPC2294 has three transmit buffers, and their status can be obtained by querying the CANSR. Data is only written to transmit buffers with available space. This step is particularly important when transmitting large amounts of data; otherwise, transmission reliability cannot be guaranteed. After successful transmission, the success of data transmission can only be determined by querying the TCS bit of the CANSR or configuring a successful transmission interrupt. 2.3 Data Reception Data can be received using either polling or interrupt methods. The CAN bus is not always active for a certain period; to improve efficiency, interrupt methods can be used. The receive interrupt must be enabled in the initialization program. In the interrupt service routine, the CANICR is read to check for a receive interrupt flag; if present, the receive buffer data is read. To prevent receive buffer overflow, a circular receive data queue can be created to temporarily store data, and the main program retrieves bus data by querying this queue. 2.4 Exception Handling In the event of a serious fault on the online bus, the CAN node may disconnect from the bus. In this case, the following register bits are set: BS bit of CANSR, BEI and EI bits of CANIR (if enabled), and RM bit of CANMOD. RM resets and disables many CAN controller functions. The software must then set the RM bit to zero. The transmit error counter will decrement the bus release condition (11 consecutive recessive bits) to the 128th event. The software can monitor the decrement of the counter by reading the Tx error counter. In applications, if previously transmitted data to the CAN controller is not read and the receive buffer is not released in time, subsequent information may be lost. In this case, the CANSR data overflow bit must be cleared by writing to the command register. Both of these exceptions can be handled through exception interrupts; simply add the handling code to the interrupt subroutine. Other bus exception handling can be handled in software depending on the usage. In short, software development and planning are crucial. The ARM7TDMI instruction set is RISC-based, featuring 32-bit ARM/16-bit Thumb dual-finger SR interoperability. Therefore, to improve code density, some code with low performance requirements can be written using the Thumb instruction set. Due to its small size, low power consumption, and good anti-interference capabilities, this solution has been applied to a vehicle communication device in a complex electromagnetic environment, meeting the project's requirements for CAN network nodes. (Edited by: He Shiping)