Using TI's TMS320C6713, the OV7620 digital image sensor chip is directly connected via address decoding and bus isolation. Leveraging the independent transmission capabilities of EDMA, real-time video image acquisition and processing are achieved without increasing DSP software overhead or bus usage. Verification shows the system features good real-time performance, low cost, and short development cycle. Bus isolation and data latching are used to interface the DSP with the low-speed LCD display module. Driver examples are provided for the specific hardware circuit. Introduction In DSP-based video processing systems, video acquisition methods can generally be divided into two categories: automatic video acquisition and DSP-based video acquisition. The former typically uses a CPLD/FPGA to control the video decoding chip, transmitting data to the DSP via FIFO or dual-port RAM. Its advantages include independent data acquisition module operation and low DSP resource consumption, but it is relatively complex to implement and has a higher cost. The latter typically uses the DSP to control the video decoding chip and synchronize various timing sequences to read video data. Its advantages include relatively simple implementation and reduced cost, but the control of the video decoding chip is more complex and consumes more DSP processing time. If the digital image sensor chip is directly connected to the DSP through appropriate logic circuits, the video control decoding chip, CPLD/FPGA, FIFO, or dual-port RAM can be eliminated. This significantly reduces system complexity and cost, and shortens the development cycle without increasing DSP software overhead. 1 Hardware System Design 1.1 System Overall Structure The system structure diagram is shown in Figure 1. The DSP uses the TI C6000 series high-speed floating-point signal processor TMS320C6713, with a peak processing speed of 1350 MFLOPS (millions of floating-point operations per second). Its external memory interface (EMIF) includes four CE spaces: CE0 is configured as a 16-bit synchronous space connected to SDRAM; CE1 is a 16-bit asynchronous space connected to Flash; CE2 is a 16-bit asynchronous space, which connects the OV7620 digital image sensor after address decoding and bus buffering; and CE3 is an 8-bit asynchronous space, which connects the LCD display module after data latching and bus isolation. 2. OV7620 Configuration and Hardware Connection The OV7620 is a CMOS color/black and white image sensor manufactured by OmniVision. In this system, it is configured as a 16-bit progressive scan QVGA sensor with RGB raw data output, a resolution of 320×240, an SCCB bus, and an internal default line exposure mode. Simultaneously, the HREF signal is enabled to gate the PCLK pin; that is, the pixel clock signal is only output to the PCLK pin when HREF is valid, otherwise the pin remains invalid. This ensures that EDMA is always enabled, simplifying the acquisition process. The hardware connection diagram between the OV7620 and the DSP is shown in Figure 2. After resetting the OV7620, the DSP configures the internal function registers of the OV7620 through GPIO simulating the SCCB bus. Afterward, the image data and synchronization signal gradually stabilize over several frames. The Y channel and U/V channel are connected to the lower 16 bits of the EMIF data bus after passing through a 74HC244 bus buffer. CE2, along with address lines EA20 and EA21, decodes to generate strobe signals for two 74HC244 chips. At this point, the read address of the OV7620 is 0xA0000000. 3. EDMA Data Acquisition In 16-bit progressive scan mode, each line of raw RGB data is output twice by the OV7620. Therefore, only the data corresponding to the even-numbered HREF signals needs to be read to obtain the entire image information. This reduces the storage space and bus resources required for image acquisition. The correspondence between OV7620 synchronization and control signals and GPIOs is shown in Table 1. This system uses the 12th channel of EDMA (EDMA12) for image data acquisition. This channel is configured for 16-bit one-dimensional transmission, interrupts are disabled, and the rising edge of PCLK triggers EDMA12 to move a 16-bit data bit into SDRAM. Each EDMA task moves one HREF (320 16-bit bits) of image data. The rising edge of the frame synchronization signal VSYNC triggers a DSP interrupt, initializes the EDMA channel, enables the horizontal reference signal HREF interrupt, and disables the EDMA channel (discarding the data from the first HREF), starting the data transmission of a frame. The falling edge of HREF triggers a DSP interrupt, marking the end of one HREF data output from the OV7620. If the next HREF data needs to be read, the interrupt service routine will correct the EDMA12 parameters, enable the EDMA12 channel, and start the transmission of the next line of data; otherwise, it will disable EDMA12 and discard the next HREF data. A total of 240 HREF interrupts and 120 EDMA data transmissions are generated for each frame of image data received. The following is a partial source code for OV7620 data acquisition: [align=center] [/align] 4. LCD Module Driver Using an LCD module allows for real-time display of image processing results, facilitating debugging and demonstration, and reducing costs. This system uses the NHC_34 color LCD display control module developed by Beijing Ninghe Electronic Technology Development Co., Ltd. This module supports 256-color display, with each pixel represented by one byte, resulting in a resolution of 320×234. It supports standard Intel 8-bit asynchronous bus timing, has two pages of display cache, and allows for arbitrary configuration of the display and operation pages. The LCD module's read/write cycle is as short as 350ns, while the DSP's external bus interface clock frequency is typically above 100 MHz, meaning it's less than 10ns. By configuring the EMIF CE3 space control register CECTL3 (address 0x01800014), the read/write cycle of the CE3 space can be extended, enabling seamless connection with the LCD module. However, this would cause the LCD module's read/write operations to occupy the system bus for too long, reducing the efficiency of accessing other memory spaces (especially SDRAM), thus affecting the overall system speed. This system employs data latching and bus buffering methods, using a 377 latch to simulate low-speed bus control signal timing and a 244 data buffer to isolate low-speed bus data. Figure 3 shows the hardware connection diagram between the DSP and the LCD module. The system has two 74HC377 chips (referred to as "377"). One chip is used to latch the read/write control signals of the analog LCD module (control 377), and the other chip is used to latch the write data (data 377). The asynchronous write enable control line AWE serves as the trigger edge input of the 377. CE3, EA20, and EA21 are decoded to generate two enable signals for the 377. The address of the DSP writing data 377 is 0xB0000000, and the address of the writing control 377 is 0xB0040000. The output of the data 377 is connected to the LCD module bus via a bus buffer HC244 (write 244, HC244 is referred to as "244"). The enable signal output of the 244 comes from the control 377. Another HC244 (read 244) is used to connect the LCD module bus to the lower 8 bits of the DSP bus. Its output enable signal is also generated by decoding CE3, EA20, and EA21, with an address of 0xB0080000, which is the DSP's read address for the LCD module. The DSP, based on the LCD module bus timing, uses timer delay interrupts to periodically write data to control 377 to simulate the control signals of the corresponding low-speed bus, and reads data from read 244 (read cycle) or writes data to data 377 (write cycle) as needed, thus completing the read/write operation on the LCD module. The LCD write cycle driver routine is as follows (this program controls the time interval through delay): 5 Software System Design The software system flowchart is shown in Figure 4. After the DSP completes the reset, it first initializes the system, configures the PLL, EMIF, and GPIO, and performs a hardware reset of the OV7620. It then configures its internal function registers by simulating the SCCB bus through GPIO, and finally clears the LCD module screen. When EDMA is not enabled, the OV7620's synchronization signal can still be captured and maintained by the EDMA event register. Therefore, EDMA initialization is placed after the initialization of the OV7620 and LCD module, and the event flag is cleared before enabling it. After the interrupt is enabled, the OV7620's frame synchronization signal will trigger a system interrupt, starting the cyclic acquisition of data. After each frame of data acquisition is completed, the corresponding flag is set to notify the main program for processing. Upon receiving the notification, the main program interpolates and smooths the raw data from the OV7620 to generate RGB 24-bit color image data to be processed. The results of image processing and calculation are sent to the LCD module for dynamic display. The LCD display task is mainly completed by the interrupt service routine, while the main program has already begun waiting for and processing the next frame of image. 6 Conclusion This system, through bus isolation and address decoding, uses only simple logic chips to connect the OV7620 to the DSP, and fully utilizes the independent transmission characteristics of EDMA, occupying only a small amount of DSP software overhead and bus resources to complete the acquisition of image data. Compared to solutions using video interface chips, peripheral FIFOs, and CPLD/FPGA, this system significantly reduces system costs and shortens the development cycle without increasing system bus usage. Data latches and bus buffers are used to enable asynchronous low-speed bus access to the LCD module; EDMA is used for bus simulation, further reducing DSP involvement in LCD module read/write operations, minimizing system interrupts, optimizing system performance, and enabling real-time and intuitive display of image processing results. Compared to other DSP embedded systems, this system features high processing speed, simple interface, low cost, and real-time display capabilities, making it suitable for applications requiring high-speed image processing, such as visual navigation and real-time video processing, as well as applications requiring real-time demonstrations. (Edited by: He Shiping)