To improve algorithm efficiency and enable real-time image information processing, this processing system is designed based on a hybrid DSP+FPGA architecture. The service board uses the FPGA as its processing core to achieve real-time image processing of digital video signals. The DSP implements some image processing algorithms and the FPGA's control logic, and responds to interrupts to achieve data communication and store real-time signals. Firstly, this system requires the DSP to meet the requirements of complex algorithm control structures, high processing speed, flexible addressing, and strong communication capabilities. Therefore, we selected a DSP with short instruction cycles, high data throughput, strong communication capabilities, and a complete instruction set. We also considered factors such as DSP power consumption and development support environment. Since the low-level A/D signal from the detector has a large data volume for its difference preprocessing algorithm, requiring high processing speed but with a simple computational structure, a million-gate FPGA was chosen for hardware implementation. The hardware system using a hybrid DSP+FPGA combines the advantages of both, balancing speed and flexibility while meeting the requirements of both low-level and high-level signal processing. Therefore, it is very suitable for real-time signal processing systems. System Architecture Design: CompactPCI, as the electrical, software, and industrial assembly standard for the PCI bus, is one of the latest computer standards today. The high speed, robustness, reliability, and stability of the CompactPCI bus, along with its excellent compatibility with PCI software, make it the most popular and universal computer interface bus in the industrial control field. CPCI currently has a maximum transmission speed of 528MB/s, while the available PCI-X can reach a maximum transmission speed of 1066MB/s. Based on this high-speed, robust, reliable, and stable technology, this system is designed with a CPCI backplane and interface system that can utilize customer-defined protocols, and a highly modular CPCI service board. Integrated Service Processing Platform : An integrated service processing platform refers to a single platform that performs tasks such as multi-channel signal preprocessing, complex image algorithms, image display, data storage, and system control. This not only requires high-performance hardware capable of real-time processing, but also demands small size, light weight, powerful functionality, and high reliability in embedded application environments. The complete system consists of the following modules: chassis, power supply, backplane, A/D preprocessing board, and signal processing board. The chassis adopts a standard 19-inch rack-mount form factor. Internal Space: Supports a 2U 4-slot CPCI backplane; supports two 3U CPCI power supplies. The rear panel features dual power input interfaces with on/off switches (supporting normally open) to respond to system restart requirements after power failure. The 3U CPCI power supplies support hot-swapping; utilize an integrated intelligent power management backplane; and support AC input. The backplane has four 6U slots, each with five sockets: P1, P2, P3, P4, and P5. P1 and P2 are standard PCI slots, providing a 5V/3.3V signal environment. System slots P3, P3, and P5 are defined according to the system board MIC-3369 standard. Expansion Slots: P1, P2, P3, P4, and P5 use through-type long pins, penetrating both front and rear, and equipped with protective sleeves. The design of P1 and P2 allows both front and rear expansion boards to draw power from the backplane as needed. P3, P4, and P5 provide complete front and rear signal routing. Furthermore, the P3, P4, and P5 slots of the three expansion slots are designed with pin-to-pin connections. This design establishes linear expansion between service boards, creating physical communication ports between higher-level processing modules and lower-level modules. Considering that each service board in the system needs to handle multiple inputs and that convenient installation is required, we specifically designed a standard processing module for analog input signal conditioning: a 233.35mm x 80mm x 1 slot. This allows all signal lines to be connected at the rear of the enclosure. Each service board's pre-processed digital signal is transmitted at high speed via P5 to the corresponding FIFO on the service board according to a predetermined method. The FIFO controller changes its operating mode based on the validity of the trigger. For ease of system expansion and troubleshooting, the service processing boards are designed with a unified architecture. This means that users only need to modify the designed software kernel for different processing services; the hardware interface program and user interface remain unchanged. Similarly, troubleshooting only requires replacing the faulty service board. The service processing board measures 233.35mm × 160mm × 1 slot; it supports the PICMG 2.1 hot-swappable specification. Both the DSP and FPGA on the board have their own RAM for storing data required for service processing. PMC I/O Expansion Board: In practical engineering applications, modular system components often need to accept external commands or output data through specific I/O interfaces. We use PMC cards to address this. The PMC (PCI Mezzanine Card) specification IEEE 1386 provides a standard for mezzanine modules. It offers a cost-effective way to implement I/O functions for different carrier board specifications. The PMC standard maps PCI bus signals onto the PJ386 board. The single-module size (74mm × 149mm) features a protruding section at the front for I/O connectivity, interconnecting with the PCI on the carrier board via four connectors labeled P1, P2, P3, and P4. Users can select a standard PMC network interface card for receiving and transmitting data according to site requirements. Various customized serial I/O interface cards can also be used to complete timing and scheduling. The system processing board MIC-3369 employs a low-power Pentium-M processor and an optimized Intel*E7501+ICH4R chipset, featuring a 64-bit/66MHz system bus and providing a bandwidth of 3.2GB/s, offering highly competitive performance. The MIC-3369 is designed to support the PICMG 2.16 specification and is compatible with PICMG. The 2.9 specification enables collaborative operation with remote management system platforms. The system utilizes a (far)infrared telemetry system to perform real-time processing of infrared digital video signal imaging. For remote sensing observation of large-scale spaces or complex terrains, detectors across multiple infrared frequency bands are employed. Data is processed according to different precision levels, images are plotted and output to a display terminal, and large amounts of data are rapidly stored on the local hard drive for later use. The system's working principle is illustrated in Figure 4. Real-time Target Detection System Industrial video processing systems are used in IC manufacturing and precision component grinding. In such systems, the parallel input/output signal frequency is generally not high, but the requirements for signal processing accuracy and real-time performance are very stringent. We implemented a real-time target detection system using the above architecture. The system's main tasks are to receive grayscale images from multiple workstations, including position sensors, displacement sensors, and cameras; perform preprocessing, encoding, algorithm processing, and target recognition; output the results to a display terminal; and simultaneously send commands to the control circuit. The lower-level processing involves a large amount of computational data but has a relatively regular computational structure, making it suitable for pure hardware implementation using an FPGA. Higher-level image processing, such as algorithm processing and target recognition, requires various protocol structures and is implemented using DSP programming. Conclusion The architecture described in this paper enables the rapid implementation of high-density, high-reliability systems on an open, modular platform. It features: 1. Low MTTR and high availability; 2. Flexible system configuration and convenient upgrades and maintenance; 3. Easy system customization, reducing R&D costs; 4. Rapid implementation of dedicated applications, enhancing competitive advantage. Editor: He Shiping