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Design of a digital capacitance meter

2026-04-06 06:06:41 · · #1
Abstract: In real life, there are many times when it is necessary to measure capacitance without instruments. This paper presents a digital capacitance meter that can measure capacitance independently. The purpose of this design is to independently complete a design project by applying the theoretical knowledge of digital circuit courses. Through the analysis and comparison of actual circuit schemes, design calculations, component selection, installation and debugging, we will initially master the analysis methods and engineering design methods of simple and practical circuits. In the design process, our design tasks and requirements are: 1. To realize the basic function of capacitance measurement; 2. To realize the digital display of capacitance; 3. To realize the range measurement function, which can measure capacitance over a large range; 4. Accuracy requirements. In this way, our capacitance meter can not only realize the function of measurement but also read the measurement results very conveniently. [b]I. Scheme Selection[/b] For a capacitor with a constant capacitance, as long as the external charging circuit parameters are determined, the charging and discharging time is uniquely determined. Here, we can use the charging time of the capacitor to control the counter counting. The charging time of the capacitor is used as the gate signal, and the width of the reference pulse provided by the reference pulse generator is used as the measurement modulus. In this circuit, the pulse width TS = 100s (100KH) represents the capacitance of 1pF. During the charging time of the capacitor under test, the gate is opened when the capacitor under test starts charging and closed when charging ends. During the gate opening time, the number of basic pulses counted by the counter multiplied by the modulus is the capacitance. Changing the order of magnitude of the charging and discharging time can change the range of the measured capacitance. The gate controller can be constructed using capacitors and resistors to form a charging and discharging circuit. The charging waveform is shaped using a shaping circuit composed of a 555 timer. The shaped signal is used to control the timing of the reference pulse to provide counting pulses to the counter. The reference signal can be constructed using a 555 integrated circuit, and the counter can be constructed using a decimal adder counter. The output of the counter is then displayed through a decoding circuit. From the above analysis, it can be seen that this method of measuring capacitance is reasonable, and it can meet the accuracy requirements of general amateur measurements. Therefore, we choose this scheme as the design scheme. II. Design Steps 1. The preliminary design can be summarized from the previous analysis as follows: our design principle should consist of six parts: reference pulse generator, gate control circuit, counter, decoder, charging and discharging circuit, and display. (1) Charging and discharging circuit: For this design, the charging and discharging circuit plays a significant role in determining the accuracy of the capacitance measurement results. Therefore, we first design the capacitor charging circuit and choose the simplest circuit. However, the output of this circuit does not have good edges and cannot accurately express the charging time of the capacitor, nor can it accurately control the gate circuit. Therefore, we consider using a shaping circuit. Here, we choose a monostable circuit composed of 555 integrated circuits for shaping. After shaping, the signal is output from the out pin of the 555 integrated circuit. We performed simulation on EWB and observed that the waveform has been significantly improved. (2) Reference pulse generator circuit: The reference pulse is used as the CP of the counter, so a general multivibrator and shaping circuit can be used. Since we choose a relatively high frequency (100KHz) as the counting frequency, we choose a quartz crystal to form an oscillator in order to make the frequency more stable. From the simulation waveform, the pulse wave generated by the reference pulse generation circuit is not very close to the ideal square wave, but it is perfectly acceptable to use it for the CP of the counter. (3) Counter circuit In order to meet the range and accuracy requirements, we need four-bit output. We choose to use four 74LS160 decimal counters to make the counter. In order to ensure the accuracy of counting during the design process, the 160 counter cannot start counting from the beginning. It should be asynchronously set to 0 at the beginning. Therefore, a start control signal should be added to the CD terminal. In the design process, we did not add the three NOT gates in the circuit at the beginning, but found that a carry occurred when the low bit was 9. In order to eliminate this error, we added the three NOT gates to the carry signal to generate a delay, so that the display error will not occur. (4) Gate control circuit According to the theory, the shaped waveform is a signal with one positive jump. We invert this signal. When the capacitor is charging, the output is kept at 1. After charging is completed, it is kept at 0. The signal is ANDed with the basic pulse, and the obtained signal is used to control the counter to count. (5) Decoder and display For ease of manufacture and operation, we selected 4 CH283L register-decode-digital display chips, so that decoding and display are completed by the same device. 2. Design and calculation From the above analysis, it can be seen that the circuit composition is also changed to seven parts: reference pulse generator 108, start control, gate control circuit, counter, decoder, shaping circuit, display, charging and discharging circuit. (1) Start control circuit In order to synchronize the counting and gate control signals, the start control circuit is designed. That is, the start circuit should give a negative pulse to control the counter to be asynchronously reset to zero, and at the same time start the monostable trigger. Therefore, the start control circuit is formed by a low frequency oscillator with a frequency of: f=1.443/(R2+2R.)C. ≈0.15KH. After the power is turned on, the circuit starts to oscillate. The first pulse resets the counter to zero and at the same time, through C, the monostable trigger is started. (2) Gate control circuit Here we combine the capacitor charging and discharging circuit and the shaping circuit into a gate control circuit. The gate circuit and its charging circuit resistor are the main components, together with the 555 timer circuit, to form a pulse-started monostable trigger. The monostable time td of the monostable trigger is 1.1RC. The measured capacitor c and the charging resistor R determine the control time of the gate circuit and the number of pulse counters counting the reference pulses. Since each pulse represents 1pF of capacitance, the more pulses measured, the larger the capacitance of the measured capacitor. In order to make the time constant RC of the measured capacitor equal to the measured modulus (10os) when C=1pF, the resistor needs to be calculated: R==9.1MtQ where c is 1pF. (3) Other circuits In addition to the two functional circuits above, the other functional circuits have been completed above, mainly including: control gate circuit, reference pulse generation circuit, pulse counting circuit, and display circuit. (4) Digital capacitance meter circuit After designing the functional circuits of the digital capacitance meter above, the overall circuit diagram can be obtained by combining the functional circuits. This design certainly has shortcomings and errors in theory, and I sincerely ask everyone to give their criticism and corrections. References: [1] Jia Xiumei. Digital Circuit Practice Technology [M]. China Science and Technology Press, 2000. [2] Xiao Jinghe. Digital Integrated Circuit Application Essence [M]. People's Posts and Telecommunications Press, 2002. [3] Wang Yuyin. Digital Circuit Logic Design [M]. Higher Education Press, 2002. [4] Sheng Guangji. 100 Examples of Practical Digital Logic Circuits [Ivf]. Shanghai Jiaotong University Press, 1991. [5] China Metrology Press (ed.). General Digital Circuits [M]. China Metrology Press, 2001. Click to download: On the Design of Digital Capacitor
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