Abstract: This paper departs from the conventional method of initializing and configuring chips using a standard 51 microcontroller. Instead, it employs a new type of microcontroller, the C8051F040, to initialize the SAA7113 decoding chip. The paper provides the configuration values ​​for each register of the decoding chip and the usage method of the C8051F040's dedicated SMBUS bus. The SMBUS bus is compatible with the IIC bus, and the C8051F040 has a dedicated SMBUS bus interface. This eliminates the need to simulate the IIC bus using microcontroller pins; data transmission only requires operations on its registers, significantly saving hardware resources and simplifying programming. Keywords: video decoder; SAA7113; C8051F040; SMBUS bus Abstract: The video decoder chip SAA7113 is initialized by the Single Chip Microcomputer C8051F040 which is a new type MCU instead of the standard 51 MCU. The paper introduces the configuration of the various registers in the video decoder and the use of SMBUS which is exclusive in the Single Chip Microcomputer C8051F040.SMBUS is compatible with IIC,C8051F040 uses exclusively interface of SMBUS instead of the analog IIC in the standard 51 MCU. SMBUS only operates its registers to save the hardware resources and to make programming conveniently when it transmits the data. Key words: video decoder; SAA7113; C8051F040; SMBUS The SAA7113 is a 9-bit video analog-to-digital converter (ADC) chip from Philips Semiconductors. It is used in many video products such as TV tuner cards, MPEG2, and MPEG4, and can also be used in video intercoms, video doorbells, and video phones. The main function of the SAA7113 is to decode the input analog video signal into a standard "VPO" digital signal. The SAA7113 is compatible with various global video standards and can be configured to the corresponding video standard as needed (initialization). Otherwise, the SAA7113 will not output as required. In my country, it is conventionally configured as PAL. Initialization of the SAA7113 requires the IIC bus. This article uses the C8051F040 microcontroller for initialization and control. The C8051F040 microcontroller is a type of 51 microcontroller, but it differs from ordinary 51 microcontrollers. It has a dedicated IIC interface, requiring only operation of specific SMBUS bus registers, making programming convenient. 1. Basic Principles and Register Introduction of SAA7113 The SAA7113 is a video decoding chip that can simultaneously input 4 channels of CVBS or 2 channels of S-video (Y/C) signals. Different configurations of its internal registers allow for input switching. The output is an 8-bit "VPO" digital signal in standard ITU656, YUV 4:2:2 format. The SAA7113 is compatible with multiple standards such as PAL, NTSC, and SECAM, and can automatically detect a field frequency of 50 or 60Hz, switching between various standards through different register configurations. The SAA7113's register addresses start from 00H and end at FFH. 00H, 1FH, 60H～62H are read-only registers and cannot be written; 14H, 18H～1EH, 20H～3FH, 63H～FFH are reserved addresses; only the following registers can be read and written: 01H～05H (front-end input channel part), 06H～13H, 15H～17H (decoding part), 40H～60H (normal separation data part) [1]. The configuration values ​​for each register are as follows [2]: Register address: 01H,02H,03H,04H,05H,06H,07H,08H,09H,0AH,0BH,0CH,0DH,0EH, 0FH,10H,11H,12H,13H,15H,16H,17H,40H,41H～57H,58H,59H,5AH,5BH,5EH Register configuration value: 08H,0C0H,33H,00H,00H,0EBH,E0H,0B8H,01H,80H,47H,42H,01H,01H 0FH,00H,0CH,0A7H,00H,00H,00H,00H,02H,FFH～FFH,00H,54H,07H,83H,00H 2. Interface Design between SAA7113 and Microcontroller C8051F040 The C8051F040 sends the configuration values ​​of each register of the SAA7113 to the decoding chip SAA7113 via the SMBUS (System Management Bus) bus (a data bus compatible with IIC). The interface circuit design between the microcontroller C8051F040 and the SAA7113 is shown in Figure 1. [align=center]Figure 1 Interface Diagram of SAA7113 and C8051F040[/align] The C8051F040 microcontroller has standard 8051 ports (0, 1, 2, and 3) and four additional 8-bit ports (4, 5, 6, and 7), for a total of 64 general-purpose I/O ports. These ports operate similarly to the standard 8051, but with some improvements. Each port can be configured as push-pull or open-drain output. A digital crossbar switch is also introduced, a large digital switch network that allows internal digital system resources to be mapped to the port I/O pins of P0, P1, P2, and P3. This feature allows users to select the combination of general-purpose port I/O and required digital resources according to their specific needs. By configuring port I/O cross switch register 0 - XBR0 = 0x01 and port I/O cross switch register 2 - XBR2 = 0x40, the P0.0 and P0.1 pins of the microcontroller are used as the SDA (Serial Data) and SCL (Serial Clock) pins of the SMBUS bus, respectively. 3. SMBUS bus timing SMBUS is a bidirectional two-wire bus developed by Intel. Its I/O interface has only two wires: SDA and SCL. SCL transmits the bus clock, and SDA transmits the bus data. The C8051F040 SMBUS bus conforms to the SMBUS VL1.1 specification and is compatible with the IIC bus [3]. The SMBUS interface can be configured to work in master mode or slave mode. Its transmission mode can be divided into four modes: master send, master receive, slave send, and slave receive. In this system, the microcontroller sends data to the SAA7113 as the master. Serial data is sent on SDA and serial clock is output on SCL. This article only gives a schematic diagram of the microcontroller sending as the master as shown in Figure 2. [align=center]Figure 2. Schematic diagram of host transmission[/align] Access and control of the SMBUS serial interface are implemented through five special function registers: control register SMB0CN, clock rate register SMB0CR, address register SMB0ADR, data register SMB0DAT, and status register SMB0STA. The SMB0STA register obtains transmit and receive information to control the data transmission process; SMB0DAT receives and transmits data; and the SMB0ADR register configures the slave's own address. In this system, SMB0ADR is configured to address 0x4a of the SAA7113, SMB0CR is configured to 0x40, and the initial value of SMB0CN is configured to 0x40, that is, enabling the SMBUS bus and setting the initial bus state to idle. 4. Software Design Before transmitting, the host first checks the BUSY (SMB0CN.7) bit. If this bit is 0, the bus is idle, and the host can occupy the bus; otherwise, it indicates that the bus is busy, and the host can continue to check this status until BUSY=0. The master generates a start condition by setting STA (SMB0CN.1) to 1. After the start condition is sent, an interrupt is generated. In the interrupt, the master checks the value of SMB0STA. If SMB0STA = 0x08, it indicates that the start bit was successfully sent. At this time, STA is set to 0, and the slave address and write control bits are sent to SMB0DAT. Then, SI (SMB0CN.3) is set to 0. The data in SMB0DAT is sent out in descending order of high-order bits. The slave receives the address and compares it with its own address. If they match, an ACK signal is generated. The master generates an interrupt, checks the value of SMB0STA, and if SMB0STA = 0x18, it indicates that the slave address and write control were successfully sent and an acknowledgment signal has been received. At this time, the master loads the data to be sent into SMB0DAT and sets SI to 0. The slave receives the data and generates an ACK signal. The master interrupts, checks the value of SMB0STA, and if SMB0STA = 0x28, the master's previous data transmission was successful. If the host has not finished sending, continue sending; if sending is complete, set STO (SMB0CN.4) to 1 to end the transmission. The workflow diagram is shown in Figure 3, where aa[k] is the data to be sent by the host. [align=center] Figure 3 Workflow Diagram[/align] 5. Simulation Results Simulation was performed using the Keil3 simulator, and single-step execution was performed to check the values ​​in each SMBUS register at any time to ensure data transmission. Figures 4, 5, and 6 show the simulation results of successful data start bit transmission, successful transmission of address and write control bits, and successful data transmission, respectively. 6. Conclusion The SAA7113 is used in many products. This system initializes it using a C8051F040 microcontroller, eliminating the need for data transmission via an analog IIC bus, saving resources, and this has been verified in actual experiments. References [1] Zhang Xiaojian. Initialization and control of video decoding chip SAA7113 [J]. Electronic Design Application, 2003, (8): 84-85 [2] SAA7113H Product specification/Data sheet. PHILIPS, 1999 [3] Tong Changfei. Development of C8051F series microcontrollers and C language programming [M]. Beijing: Beijing University of Aeronautics and Astronautics Press, 2005