Abstract: This paper introduces the IDT7005 chip, and describes the interface circuit of a CNC motion control card based on the IDT7005 chip and the control circuit program design of ispGAL20V8B. Keywords: Dual-port RAM; CNC motion control card; Interface circuit design In high-speed microcontroller data acquisition and processing systems, with the increase in the amount of acquired data and data processing tasks, the requirements for data transmission are also increasing. Serial transmission of data using the microcontroller's built-in serial port is no longer sufficient; high-speed parallel data transmission is necessary. Dual-port RAM can easily form a high-speed data transmission medium under various operating modes, solving the bottleneck problem caused by low-speed data transmission. Whether it's data sharing in parallel processing networks or high-speed data transmission in pipelined methods, dual-port RAM plays an important role in ensuring smooth data flow. I. IDT7005 Chip In addition to data storage, dual-port RAM provides two completely independent ports, each with its own control lines, address lines, and I/O data lines, allowing simultaneous reading and writing of data on both ports. This is suitable for two microcontrollers to share memory space via a bus. The IDT7005 is a high-speed 8kb eight-bit dual-port RAM device manufactured by IDT Corporation. It features fast access speed, low power consumption, fully asynchronous operation, and a simple interface circuit. The IDT7005L has a fully symmetrical structure at both ends (i.e., two completely independent sets of I/O control lines, address lines, and data lines) and an arbitration interrupt semaphore logic module, making the IDT7005L a true dual-port RAM. It allows two controllers to simultaneously read any memory cell, but does not allow simultaneous writing or one-to-one reading and writing to the same address cell. The internal functional structure of this chip is shown in Figure 1. II. Hardware Circuit Interface Design 1. Semaphore Token Passing Method of IDT7005L Since the IDT7005 has two independent bus structures, various methods can be used to solve the contention problem for the same cell on both sides. Generally, the BUSY signal of dual-port RAM can be used. However, when both ports simultaneously access data to the same address cell, one port is in a waiting state. For high-speed data transmission, inserting a waiting state will reduce data transmission efficiency, which is unacceptable in some cases. In this case, the semaphore circuit provided by the IDT7005L can be used. Here we introduce the most commonly used flag signal token passing method. The flag signal operation of IDT7005L is shown in Table 1. IDT7005 has eight latches independent of the memory unit, which can divide the 8kb memory unit into eight parts, which can be used to indicate whether the corresponding shared RAM is being used. When one side port accesses the shared RAM, it first writes "0" to the corresponding latch logic unit. If "1" is read, it means that the shared RAM is being occupied by the other side until the other side port releases the token. At this time, the data read is "0", and the corresponding RAM can be accessed. In addition, it is worth noting that when operating the flag signal, you should write first and then read, and do not read first and then write, so as to avoid the phenomenon of contention for the system bus. 2. Overall design scheme The host computer of the interface circuit design adopts an industrial control computer, and the AT89S52 microcontroller is used as the slave computer. The overall communication scheme between the ISA bus and the dual-port RAM and the dual-port RAM and the microcontroller is shown in Figure 2. (1) IDT7005 chip interface design. Since the shared RAM uses memory addressing and the latch logic unit of the semaphore token uses I/O addressing, the SMEW signal and the IOW signal are ANDed together and then sent to the R/WR signal of the IDT7005. Similarly, the SMER signal and the IOR signal are ANDed together and then sent to the OER signal of the IDT7005. When accessing the shared RAM and the semaphore token, the chip select signals are CE and SEM respectively. The A0 to A12 of the ISA bus are connected to the A0R to A12R of the IDT7005 as address lines, and the A13 to A19 are connected to a set of input terminals of the GAL20V8B. In this experiment, the shared RAM can be configured at D0000H to DFFFFH, and the semaphore token can be configured at 300H to 3FFH. (2) Programming of the read and write control circuit of ispGAL20V8B. The general-purpose array logic GAL consists of three parts: a programmable AND array, a fixed (non-programmable) OR array, and an output logic macrocell (OLMC). GAL chips require programming via GAL development software and hardware to function as intended. The GAL20V8B has eight I/O ports, 14 input ports, and 10 register units, with a maximum frequency exceeding 100MHz. It controls the soft connections of the programmable array area through programming to implement the required logic circuits. The GAL20V8B chip is used on the ISA bus interface card to implement functions such as memory address range selection, I/O address selection, address bus and data bus gating control, and control signal generation between the ISA bus and dual-port RAM. The program for the control logic used in this system is as follows. MODULE IDT7005 // Start of module IDT7005 TITLE 'IDT7005' // Title statement ADA PIN 15; IOW,IOR,SMEMW,SMEMR PIN1,2,4,5; // Input pin descriptions A14,A15,A16,A17,A18,A19PIN7,8,9,10,11,13; K1,K2,K3,K4PIN23,22,21,20; OE,CE,RW,SEMPIN18,19,17,16; S1= [A14,A15,A16,A17] ; // Address decoding combination S2= [K1,K2,K3,K4] ; EQUATIONS // Logic equation description WHEN (S1==S2) THENADA=1 ELSEADA=0; ! CE = ! (SMEMW&SMEMR) &ADA&（A18&A19） ; ! SEM=! （IOW&IOR） &! （! A18#A19） ; RW=SMEMW&IOW; OE=SMEMR&IOR; END //The pin function diagram of the IDT7005 module after programming is shown in Figure 3. III. Conclusion The design of the microcontroller-host computer data communication interface circuit and its ISA mode application through dual-port RAM were presented. The IDT7005 chip was used to realize the master-slave processor communication of the CNC machine tool motion control card. Experiments show that compared with serial and parallel communication, this method has the advantages of high speed, high data transmission reliability, strong anti-interference ability, and simple implementation, and has strong practical application value.