Abstract: An FPGA-based motion control card employs a pulse-plus-direction closed-loop control method, offering advantages such as simple structure, high integration, and good real-time performance. This paper describes the design and development of the motion control card from the perspectives of hardware composition, design, and algorithm implementation. The main hardware logic and algorithms of the system are implemented by programming the FPGA using the hardware description language VHDL (Very High Speed Integrated Circuit HDL) and schematic diagrams, thereby improving the system's flexibility and portability. In terms of hardware algorithms, ping-pong operation is used to process high-speed frequency division multiple data streams, improving the system's real-time performance and control accuracy. Furthermore, a frequency division algorithm based on a two-counter is proposed to achieve arbitrary frequency division multiples. The motion control card is debugged and simulated using the embedded debugging tool SignalTap, and corresponding error analysis is presented.
Keywords: Motion control card; Servo motor; Frequency division; Field-programmable gate array; Peripheral component interconnect standard bus; Real-time; Ping-pong operation
Design and realization of motion-controlling-card based on FPGA LI Mu-guo, PENG Ping-liang
0 Introduction
Traditional motion control cards mostly use microcontrollers as microprocessors, controlling servo motors through large-scale integrated circuits. Due to their complex structure, they suffer from drawbacks such as slow high-frequency response and low control precision. This paper proposes a motion control card with an FPGA (field-programmable gate array) and a PCI9054 interface chip as its core hardware. The internal hardware interface and algorithms are implemented through FPGA programming. This approach effectively overcomes the shortcomings of traditional motion control while significantly improving flexibility and portability.
1 Hardware Composition and Design
1.1 Composition
The motion control card described in this paper is a PCI (peripheral component interconnect) interface card [1]. An FPGA of model EP1C6Q240C8 manufactured by Altera is used as the programming logic device to implement all hardware algorithms and the detection of feedback signals. The motor is controlled by a closed-loop control method of pulse plus direction [2]. The entire motion control card system can be described by Figure 1.
1.2 Design
When describing and designing the hardware circuit of the motion control card, the synchronous timing design principle is strictly followed [3]. Moreover, the core circuit is implemented with D flip-flops, and the main signal of the circuit is generated by the rising edge of the clock flip-flop. This can avoid glitches well, and there are no glitches in the simulation after layout and the actual working signal sampled by the high-speed logic analyzer. In the control of the high-speed changing frequency division multiple data stream, in order to ensure the real-time output of the frequency division of the entire system, the "ping-pong operation" technique shown in Figure 2 [3] is adopted. In the odd number (2n+1) buffer cycle, the input data stream is buffered to RAMⅠ and the data is taken from RAMⅡ to the arithmetic module. In the even number (2n) buffer cycle, the data stream is buffered to RAMⅡ, and the data in RAM1 is sent to the final frequency division and counting arithmetic module for calculation output through the selection of the "data output selection unit". This cycle repeats. This pipeline algorithm can complete the seamless buffering and processing of data.
The motion control card described in this paper involves four modules: bus controller, frequency divider, timer, and feedback control. Its schematic diagram is shown in Figure 3. The bus controller completes the arbitration logic [5], address decoding, and data flow control of the PCI9054 [4] local bus, so that the data on the PCI data bus is correctly decoded to each sub-control module for calculation and output. The timer realizes hardware timing. The computer inputs a time value and a control word indicating the start of timing to the motion control card through the driver program. The motion control card starts timing. When the timing is completed, it enters the interrupt service routine by generating a hardware interrupt [6], thereby realizing accurate positioning of the motor's rotation angle. We can also use some user code as an interrupt handling subroutine to realize the function of timing switching or calculation. The frequency divider realizes the frequency division of the working frequency (40MHz) to obtain the pulse frequency for controlling the motor speed. The feedback control module realizes the output compensation and status monitoring functions of the motor. It can be corrected by reading the error, thereby improving the system control accuracy. These modules are described within the FPGA using a combination of schematic diagrams and VHDL, making the logic hierarchy clearer and more readable.
2 Algorithm Design
2.1 Real-time frequency division algorithm
The motor speed is controlled by different pulse frequencies output by the motion control card; therefore, the response speed of the pulse frequency determines the overall control accuracy of the motor. This necessitates that the real-time performance of the frequency division algorithm be fully considered when designing the algorithm. This paper proposes a frequency division algorithm based on a counter that increments by two, which can effectively solve this problem. The specific flowchart of the algorithm is shown in Figure 4. The phase-locked loop output clock is taken as the global clock of the design, and two single-port RAMs are used to cross-refresh the frequency division factor. The counter increments by two counts the rising edge of the input clock and compares the count value. If the count value is greater than or equal to twice the frequency division factor, the output is '1'; otherwise, it is '0'. This implements the frequency divider function. The output of the frequency divider is the pulse (clk_out) used by the motion control card to control the motor speed.
2.2 Closed-loop control algorithm
The entire motion control card employs a pulse-plus-direction control method to control the motor's speed and direction. To ensure motor control accuracy, while the motion control card outputs pulses to the motor driver, it simultaneously reads feedback pulses and direction information from the encoder. Thus, by designing two counters to simultaneously count the output and feedback pulses, and then judging and calculating the difference between the two counter values, and finally performing cyclic interpolation based on the calculated difference, closed-loop control of the motor can be achieved.
3. Debugging and Result Simulation
3.1 System Debugging
This card uses SignalTap II[7], which comes with Quartus II software, for simulation and debugging. It is an embedded logic analyzer based on a logic analysis core. When using it, the debugging personnel do not need to connect external special instruments. They can realize the analysis and judgment of system faults by capturing all signals and nodes inside the FPGA device. The whole debugging process is very intuitive and convenient. SignalTap II collects data at the rising edge of the acquisition clock. If the acquisition clock is not set properly, sometimes the data state that does not accurately reflect the design will be obtained. Altera recommends that the global clock should be used. The paper gives the global clock gclk as the acquisition clock, level 1 trigger, and RESULT = ELD({HOLD,1}) as the trigger logic[8]. The running analysis results are shown in Figure 5. It is worth noting that after debugging, the SignalTap II file should be removed from the design directory to avoid wasting resources.
3.2 Debugging Results and Error Analysis
As shown in Figure 5, the entire control of the motion control card follows the bus arbitration logic. Data exchange between PCI and FPGA occurs when READY=0, and data on the bus LD is valid when READY=0. Changing the value of the frequency divider register immediately changes the frequency divider output frequency, meeting the design goals. The system detects and judges external signals such as motor travel (journey1 and journey2), alarm, zero position, and servo. It also detects and counts the feedback clock. Since data exchange between PCI and FPGA occurs on the rising edge of the system clock, there will inevitably be a delay error of less than one clock cycle during the data exchange process.
4. Conclusion
The motion control card described in this article has the following characteristics:
① The data input and output ports adopt optical isolation technology [8] to avoid some unnecessary interference;
②The FPGA adopts an independent 40MHz clock and phase-locked loop design to ensure the system clock stability;
③ The frequency division algorithm is adopted to improve the real-time performance of the frequency division output;
④ FPGA, as the core processing chip, reduces hardware costs, simplifies hardware design, and improves real-time performance;
⑤ The motor's status is detected and error is corrected through the status detection and feedback module;
⑥ Design an interrupt timing module to realize motor rotation angle control.
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