In the production and processing of dyeing and printing machinery, each transmission unit is driven by an independent motor. To ensure the synchronous and coordinated operation of all units and improve product quality, a corresponding synchronous controller needs to be designed. Multi-unit synchronous transmission is the key to the synchronous control of dyeing and printing machinery. However, due to the severe nonlinearity of AC motors, the dynamic characteristics and corresponding parameters of the system are affected by external disturbances, increasing the difficulty of actual synchronous control and reducing the actual control accuracy. Traditional control schemes, such as synchronous systems with switching tensioners, have poor reliability and low control accuracy, making it difficult to achieve satisfactory control results. Furthermore, because the system requires rapid synchronous dynamic tracking, large overshoot is not allowed. Therefore, an embedded controller based on DSP and FPGA is proposed to improve the system's dynamic tracking speed and synchronization performance. This control device can be directly embedded into the electronic control unit to complete the control function in real time and with high performance. 1. Overall Control Strategy of the System Most dyeing and printing equipment adopts a multi-unit synchronous drive system in combination according to process requirements. The speed of the master motor serves as the given speed for each slave motor. Each slave unit is driven by its own asynchronous motor. The system requires that all unit motors maintain synchronous operation, that is, the linear speed of each slave motor always remains consistent with the speed of the master motor, or maintains a certain proportional relationship. To verify the feasibility of the control scheme, a dual-unit (master motor and slave motor) AC synchronous drive system was studied as an example. The block diagram of the dyeing and printing equipment control system is shown in Figure 1. The master motor and slave motor are powered by frequency converter 1 and frequency converter 2, respectively. A photoelectric rotary encoder is installed coaxially. The photoelectric rotary encoder converts the speed signals of the master and slave motors into pulse signals and sends them to the controller for processing. After the control algorithm, the digital control quantity is output to the frequency converter of the slave motor to change its operating frequency and adjust the speed of the slave motor to keep it synchronized with the master motor. From the above analysis, it can be seen that keeping the master and slave motors synchronized is the key to the controller design. The core of the controller consists of a 16-bit microprocessor (DSP) and a field-programmable gate array (FPGA). The embedded synchronous controller based on DSP+FPGA features flexible structure and strong versatility, making it suitable for modular design and significantly reducing the number of peripheral components and lowering costs. The DSP, as the core of the arithmetic control, mainly handles motor start/stop, control algorithm implementation, and various interface processing; the FPGA, as the core of the data acquisition module, is responsible for data acquisition and keyboard interface circuit implementation. To ensure synchronized and coordinated operation of all units in the dyeing and printing equipment and improve system response speed, a dual-mode control method is adopted for the linear speed of each unit's motor, combining Bang-Bang control with PID control. When |e| > δ (δ is a constant), Bang-Bang control is implemented to quickly bring the adjustment parameter close to the given value; when |e| < δ, digital PID control is implemented to eliminate system adjustment deviations. This speeds up the control process while ensuring minimal system overshoot, resulting in good dynamic performance. 2. Main Hardware Components of the System The hardware structure of the embedded controller is shown in Figure 2. The DSP is the core unit of the system. It performs calculations, analysis, and display on various acquired parameters and can communicate with local instruments with a 485 interface via a communication module. The TI TMS320LF2407A DSP chip is selected. It employs high-performance static CMOS technology, has a power supply voltage of 3.3V, low power consumption, and an execution speed of 30 MIPS, shortening the instruction cycle to 33 ns and improving the real-time control capability of the controller. It also has 32 KB of on-chip FLASH program memory. The 16-bit TMS320LF2407A DSP chip features fast sampling speed, high floating-point processing speed, and good stability. The DSP's special structure and excellent performance meet the system requirements. The FPGA uses Altera's FLEX series chip EPF10K10LC84, which features high density, low cost, and low power consumption. It supports multiple voltage I/O interfaces and is developed based on programmable logic devices such as PAL, GAL, and EPLD, making it very suitable for sequential and combinational logic circuit applications. The FPGA is used as an external coprocessor, connected to the DSP processor via a bus, primarily implementing functions such as pulse counting and keyboard scanning. The biggest advantage of FPGAs is the online reconfigurability of their internal logic. When application requirements change, the FPGA can be reprogrammed to alter its logic behavior, greatly improving the system's openness and reconfigurability. The high speed and flexibility of the FPGA also ensure the system's real-time performance and simplify the peripheral circuitry, reducing costs. The display module uses a G35 LCD screen, connected to the DSP via a bus. By configuring relevant registers and writing and calling relevant application programming interface functions, it can display the measured parameters, operating status, and other auxiliary information. The communication module consists of an RS-485 interface circuit, which connects the controller and the frequency converter. Communication allows the controller to set and modify the frequency converter's parameters to monitor its operating status. To facilitate on-site debugging, data input, and command transmission, a 4×4 matrix keyboard is designed. Using an FPGA to implement the keyboard interface circuit saves I/O resources, reduces the processor load, and improves the overall system performance. The data acquisition module uses two rotary encoders to convert the motor speed into digital pulses. The FPGA records the pulse values, and the DSP reads the values ​​via interrupts. After processing, the control quantity U(k) is output to the frequency converter of each slave motor via the communication module. The frequency converter adjusts the speed of the slave motor, making it continuously follow the changes in the speed of the master motor to achieve synchronization. This design improves the system's flexibility and versatility, reduces development costs, and can be connected to an embedded system as an independent module. 3. Main Software Design of the System The program here adopts a modular design. The software mainly includes a main program, a data acquisition program, a communication subroutine, a display subroutine, and a dual-mode control algorithm program. The initialization program mainly completes the clearing of various registers and the initialization of timers. The data acquisition program mainly completes the measurement of the speed of each motor, and the display subroutine mainly completes the display of various input quantities and set values. The dual-mode control program is mainly used to improve the system's response speed and stability. The main program and the dual-mode control program are shown in Figures 3 and 4. 4. Experimental Verification To verify the feasibility of the control scheme, an experiment simulating the actual system was conducted in the laboratory using a dual-unit asynchronous motor (drive motor and slave motor) AC synchronous drive system as the object. The drive motor model was Y90S-4; rated power 1.1 kW; rated voltage 380 V; rated current 2.8 A; rated speed 1400 rad/min; Y connection; frequency 50 Hz. The slave motor model was Y80-4; rated power 0.75 kW; rated voltage 380 V; rated current 7 A; rated speed 1450 rad/min; Y connection; frequency 50 Hz. Two DC generators were selected, each driven by a three-phase asynchronous motor, with a rheostat box added as the motor load. Two frequency converters drove the two three-phase asynchronous motors. The photoelectric encoder converted the slave motor speed signal into a pulse signal and sent it to the controller for processing. The curves plotted after measuring the speeds of the two motors are shown in Figures 5-7. The results show that during system operation, the following accuracy of the master and slave motors is slightly worse in the low-frequency range, while the following accuracy is higher in the high-frequency range. The master and slave motors achieve good synchronization performance over a wide speed range, and the synchronization control effect during the dynamic process is also good, achieving the expected results. 5. Conclusion The research shows that after adopting an embedded synchronous controller based on DSP and FPGA, the dynamic synchronization performance of the multi-unit synchronous system is significantly improved. The system operates stably without fluctuations, meeting the control requirements for synchronous transmission of each sub-unit. It balances the requirements of fast system response and stability, and has high control accuracy, demonstrating significant application value.