Abstract: This paper introduces a hardware design scheme for a gigabit network interface camera. Utilizing the powerful programmability and parallel processing capabilities of FPGA, the network bandwidth is maximized. Winpcap is proposed for acquiring image data, effectively improving the packet capture rate. The designed high-resolution, high-frame-rate camera delivers clear and smooth images. Keywords: Gigabit network; camera; FPGA; 1 Introduction With the increasing popularity of surveillance systems in both commercial and civilian applications, surveillance cameras are widely used in various fields to safeguard public security. Video surveillance cameras are widely used in residential buildings, villas, shopping malls, and financial offices. Each different application area requires different types of surveillance cameras. Traditional surveillance cameras have low image resolution, making it difficult to meet the needs of some applications with special requirements. Utilizing networks to transmit high-resolution, high-frame-rate video images is an important concept in video surveillance systems. However, the insufficient bandwidth and slow data transmission speed of 100 Mbps networks severely restrict their application in the surveillance field. To address this problem, this paper proposes a gigabit Ethernet-based video image transmission scheme that fully utilizes the advantages of FPGA parallel processing and SDRAM high-speed caching to improve the video image transmission speed. 2. Overall Hardware Design The overall hardware framework is shown in the diagram above. The main controller FPGA uses Altera's high-performance, cost-effective EP2C20F256C6N chip. The system operates at 100MHz. Image sensor data is first buffered in a FIFO and then temporarily stored in SDRAM. When the network is idle, the temporarily stored image data is buffered in FIFO2 and sent to the MAC chip before being transmitted over the network. The CMOS chip used is Micron Technology's MT9P031, which can output up to 14 frames of image data at a full resolution of 5 megapixels. The SDRAM used is the W982516BH-75, with a capacity of 32Mbytes. Combined with the FPGA's internal FIFO, it can be designed as a large-capacity 32Mbyte circular buffer, capable of buffering more than 10 frames of image data at a resolution of 3 megapixels. The gigabit network interface MAC chip uses the AX88180, and the physical layer chip uses the 88E1111. It is then connected to the computer's gigabit network card via a network transformer and an RJ45 Cat 6 cable. 3. Gigabit Ethernet Interface Design The AX88180 is a high-performance, low-cost non-PCI gigabit Ethernet controller from AsiaInfo, suitable for various embedded systems requiring high-speed network access, such as consumer electronics and home networks. The AX88180 integrates a 10/100/1000 Mb/s Ethernet Media Access Controller (MAC), compliant with IEEE 802.3/IEEE 802.3u/IEEE 802.3ab protocols, and can connect to general 16/32-bit microcontrollers, operating identically to SRAM. The AX88180 integrates a 10/100/1000 Mb/s Ethernet Media Access Controller (MAC), which uses an RGMII interface with the PHY; it also includes a built-in host interface controller for easy connection to 16/32-bit hosts, with addressing modes similar to SRAM; it has a built-in 40 KB SRAM network packet buffer, with 32 KB used for receiving data packets from the PHY and KB for sending data packets from the host to the PHY, allowing for efficient packet storage, retrieval, and modification; it has a built-in 256-byte configuration register for host control and parameter settings; it also includes an EEP-ROM interface; and built-in IP/TCP/UDP checksums significantly reduce the microcontroller's computational load and improve transmission response time. Figure 2 shows the connection diagram of the AX88180 and the PHY chip 88E1111. 3.1 Gigabit Ethernet Interface Initialization The initialization of the Gigabit Ethernet interface is crucial; incorrect initialization will prevent the system from functioning correctly. Interface initialization mainly involves initializing the AX88180 and 88E1111. The code is implemented using Verilog. For specific code examples, refer to the driver code from AsiaInfo. Note that a fixed delay needs to be added during initialization to ensure the chip functions correctly. 3.2 Image Data Packetization When the image resolution is 2048×1536, a UDP packet contains 1024 bytes of image data and two bytes of image row numbers. When the computer receives the data packet, it places it into the corresponding memory based on the image row number information, making it easy to assemble a complete image. Furthermore, using row numbers prevents the entire image from failing to display due to the loss of one or two data packets. The following is the UDP header code written to the AX88180 by the FPGA. case (param_num) 'd0: w_dd <= 'hFFFF;//Destination MAC address (broadcast address), written three times'd3: w_dd <= 'h1111;//Source MAC address, all are 0x1111, written three times'd6: w_dd <= 'h0008;//Protocol number'd7: w_dd <= 'h0045;//Fixed data VIP4'd8: w_dd <= 'h1E04;//Total IP packet length 1026+28, and high and low 8 bits swapped'd9: w_dd <= 'h0;//ID number, always 0'd10: w_dd <= 'h0;//fragment offset always 0'd11: w_dd <= 'h1140;//Time to live and protocol number, fixed'd12: w_dd <= 'h0; //IP checksum, automatically generated by the MAC chip'd13:w_dd <= 'hA8C0; //Source IP, fixed at 192.168.1.204'd14:w_dd <= 'hCC01;'d15:w_dd <= 'hFFFF; //Destination IP, arbitrary'd16:w_dd <= 'hFFFF;'d17:w_dd <= 'h7017; //Source port, fixed at 6000'd18:w_dd <= 'h7017; //Destination port, fixed at 6000'd19:w_dd <= 'h0A04; //UDP data length'd20:w_dd <= 'h0; ////Checksum automatically generated by AX88180'd21:w_dd <= row_num; // Image row information starts from 0. default: w_dd <= w_dd; endcase 3.3 Application Design Due to the large amount of data transmitted over the network, obtaining image data packets using SOCKET is difficult, resulting in a high packet loss rate. Using Winpcap to capture network data packets can effectively reduce the packet loss rate. Writing programs using Winpcap requires installing the development kit and driver. The first step is to specify and enable the network card device to communicate with. BOOL InitWpcap() { pcap_if_t * alldevs; pcap_if_t * d; char errbuf[PCAP_ERRBUF_SIZE]; if (pcap_findalldevs(&alldevs, errbuf) == -1) { AfxMessageBox("Error in pcap_findalldevs"); return FALSE; } // Enumerate network cards and add them to the user-selected ComboBox, code omitted char *filter = "port 6000"; // Only receive data from port 6000 bpf_u_int32 NetMask = 0xFFFFFF; struct bpf_program fcode; if (pcap_compile(m_pcap, &fcode, filter, 1, NetMask) < 0) { AfxMessageBox("nError compiling filter: wrong syntax"); pcap_close(m_pcap); return FALSE; } if (pcap_setfilter(m_pcap, &fcode) < 0) { AfxMessageBox("\nError setting the filter\n"); pcap_close(m_pcap); return FALSE; } pcap_freealldevs(alldevs); // Release alldev resources return TRUE; } Step 2: Start a thread to receive data. UINT RecvProc(LPVOID lpParammeter) { pcap_loop(m_pcap, 0, packet_handler, NULL); return 0; } packet_handler is the callback function that handles received data packets. It is called after data is received from port 6000 and continues until the thread terminates. Step 3: Process the received data void packet_handler(u_char *param, const struct pcap_pkthdr *header, const u_char *pkt_data) { const u_char *real_data = pkt_data+42; int row=real_data[0]+(real_data[1]<<8); } // Here, the packet header is not processed, and the data is processed directly. 4 Summary The network transmission bandwidth of the megabit network interface camera reaches more than 400Mb/s, which effectively solves the problems of insufficient bandwidth and slow data transmission speed of 100M network. Transmitting 3 million pixel uncompressed raw images, the frame rate can reach 18 frames/second, and the video is smooth and clear. The computer uses Winpcap to capture image data, and the packet loss rate is less than 0.02%.