Abstract: Taking the PM200DSA060 intelligent power module (IPM) as an example, this paper introduces the structure of the IPM and provides the design schemes for its peripheral drive circuit, protection circuit, and buffer circuit. It also describes the application of the PM200DSA060 in a single-phase inverter.
Keywords: IPM; circuit design; PM200DSA060; inverter
1 Introduction
Intelligent Power Modules (IPMs) are increasingly widely used in the power electronics field due to their advantages such as fast switching speed, low loss, low power consumption, multiple protection functions, strong anti-interference ability, no need for anti-static measures, and small size. Taking the PM200DSA060 IPM as an example, this paper introduces the IPM application circuit design and its application in a single-phase inverter.
2. Structure of IPM
An IPM consists of a high-speed, low-power IGBT, a preferred gate driver, and protection circuitry. The IGBT is a composite of a gate-to-gate (GTR) and a MOSFET, with the GTR driven by the MOSFET. Therefore, the IPM combines the advantages of a GTR (high current density, low saturation voltage, high withstand voltage) with the high input impedance, high switching frequency, and low drive power of a MOSFET.
Depending on the internal power circuit configuration, IPMs come in various types, such as the PM200DSA060 model: This IPM is type D (integrating two IGBTs internally). Its internal functional block diagram is shown in Figure 1, and its internal structure is shown in Figure 2. It contains drive and protection circuits, with protection functions including undervoltage lockout protection, overheat protection, overcurrent protection, and short-circuit protection. When any of these protection functions activates, the IPM will output a fault signal FO.
The internal circuitry of an IPM lacks signal isolation circuitry for interference prevention, self-protection functions, and surge absorption circuitry. To ensure the safety and reliability of the IPM, some external circuitry needs to be designed manually.
3. External drive circuit design of IPM
The external drive circuit of the IPM is the interface between the internal circuit and the control circuit of the IPM. A good external drive circuit is of great significance to the operating efficiency, reliability and safety of the system composed of IPM.
As can be seen from the internal structure diagram of the IPM, the device itself contains a drive circuit. Therefore, it only needs to provide a PWM signal that meets the drive power requirements, a power supply for the drive circuit, and an electrical isolation device to prevent interference. However, the IPM has strict requirements for the output voltage of the drive circuit: the drive voltage range is 13.5V~16.5V. A voltage below 13.5V will trigger undervoltage protection, and a voltage above 16.5V may damage internal components; the drive signal frequency is 5Hz-20kHz, and an electrical isolation device is required. To prevent interference: the insulation voltage of the drive power supply must be at least twice the reverse withstand voltage between the IPM terminals (2Vces); the drive current must reach 19mA-26mA; the filter capacitor at the output of the drive circuit cannot be too large. This is because when the parasitic capacitance exceeds 100pF, noise interference may falsely trigger the internal drive circuit.
Figure 3 shows a typical high-reliability IPM external drive circuit scheme. The PWM signal from the control circuit is current-limited by R1, then amplified and isolated by a high-speed optocoupler before being connected to the internal drive circuit of the IPM to control the operation of the switching transistors. The FO signal is also output through optocoupler isolation. Each switching transistor's control power supply terminal uses an independently isolated regulated 15V power supply, connected to a 10μF decoupling capacitor (not shown in the figure) to filter out common-mode noise. R1 is selected based on the output current of the control circuit. If PWM is generated by a DSP, the resistance of R1 can be 330Ω. R2 is selected based on the IPM drive current; it should be as small as possible to avoid noise pickup by the high-impedance IPM, while still ensuring sufficient reliability in controlling the IPM. It can be selected within the range of 2kΩ to 6.8kΩ. C1 is a 0.1μF filter capacitor between terminals 2 and ground. The requirement for the PWM isolation optocoupler is tPLH 10kV/μs. High-speed optocouplers such as HCPIA503, HCPIA504, and PS2041 (NEC) can be selected, and a 0.1μF decoupling capacitor (not shown in the figure) should be connected to the input terminal of the optocoupler. The FO output optocoupler can be a low-speed optocoupler (such as PC817). The internal pin functions of IPM are shown in Table 1.
The external interface circuit in Figure 3 is directly fixed on the PCB and close to the module input pin to reduce noise and interference. The wiring distance on the PCB should be appropriate to avoid potential changes caused by interference during switching.
In addition, considering that high voltage may cause interference from the external drive circuit to the IPM lead, filter capacitors can be added between pins 1-4, 3-4, and 4-5 according to the magnitude of the interference.
4. Protection Circuit Design of IPM
Since the protection circuit provided by the IPM itself does not have a self-protection function, it is necessary to use external hardware or software auxiliary circuits to convert the internally provided FO signal into a control signal to shut down the IPM, thereby turning off the IPM and achieving protection.
4.1 Hardware
When the IPM malfunctions, the FO output goes low, reaching the hardware circuit via a high-speed optocoupler to shut down the PWM output, thus protecting the IPM. The specific hardware connection is as follows: A 3-state transceiver with a control terminal (such as 74HC245) is placed before the PWM interface circuit. The PWM signal is sent to the IPM interface circuit after passing through the 3-state transceiver. The IPM's fault output signal FO is output via optocoupler isolation and sent to a NAND gate. It is then sent to the 3-state transceiver's enable terminal OE. When the IPM is working normally, the NAND gate output is low, and the 3-state transceiver is enabled; when the IPM malfunctions, the NAND gate output is high, and all outputs of the 3-state transceiver are set to a high-impedance state. This blocks the control signals of each IPM, shutting down the IPM and achieving protection.
4.2 Software
When an IPM malfunctions, the FO output goes low. The FO signal is sent to the controller for processing via a high-speed optocoupler. After processor confirmation, the IPM's PWM control signal is shut down using an interrupt or software, thus achieving protection. In DSP-based control systems, IPM protection can be achieved using the power drive protection pin (PDPINT) interrupt in the event manager. Typically, one event manager generates multiple PWM signals to control multiple IPMs. Each switch can output an FO signal, which is passed through an AND gate. When any switch malfunctions, it outputs a low level, and the AND gate outputs a low level. This pin is connected to PDPINT. Since the DSP interrupts when PDPINT is low, all event manager output pins are hardware-set to a high-impedance state, thus achieving protection.
Both of the above schemes utilize the IPM fault output signal to block the IPM control signal channel. Thus, they compensate for the shortcomings of the IPM's own protection and effectively protect the device.
5. IPM Buffer Circuit Design
In IPM applications, the di/dt, dv/dt, and instantaneous power consumption generated by the high-frequency switching process and the parasitic inductance of the power circuit can have a significant impact on the device, easily damaging it. Therefore, a buffer circuit (i.e., an absorption circuit) is required to change the switching trajectory of the device, control various transient overvoltages, reduce device switching losses, and protect the device for safe operation.
Figure 4 shows three commonly used IPM snubber circuits. Figure 4(a) shows a snubber circuit composed of a single non-inductive capacitor, which is effective for transient voltages and has low cost, suitable for low-power IPMs. Figure 4(b) shows a snubber circuit composed of an RCD, suitable for higher-power IPMs. The snubber diode D can clamp transient voltages, thereby suppressing parasitic oscillations that may be caused by the parasitic inductance of the bus. Its RC time constant should be designed to be 1/3 of the switching cycle, i.e., r=T/3=1/3f. Figure 4(c) shows a snubber circuit composed of a P-type RCD and an N-type RCD, suitable for high-power IPMs. Its function is similar to the snubber circuit shown in Figure 4(b), but its loop inductance is smaller. If used in conjunction with the snubber circuit shown in Figure 4(a), the stress on the snubber diode can be reduced, and the snubber effect is better.
In Figure 4(c), when the IGBT is turned off, the load current charges the snubber capacitor through the snubber diode, while the collector current gradually decreases. Since the voltage across the capacitor cannot change abruptly, the rise rate of the IGBT collector voltage, dv/dt, is effectively limited. This also prevents the collector voltage and collector current from reaching their maximum values simultaneously. The energy stored in the IGBT collector bus inductance, the stray inductance within the circuit and its components when the IGBT is turned on is stored in the snubber capacitor. When the IGBT is turned on, the collector bus inductance and other stray inductances effectively limit the rise rate of the IGBT collector current, di/dt, again preventing the collector voltage and collector current from reaching their maximum values simultaneously. At this time, the snubber capacitor discharges through the external resistor and the IGBT switch, and the stored switching energy is dissipated through the external resistor and the resistors within the circuit and its components. In this way, the switching losses generated during IGBT operation are transferred to the snubber circuit and finally dissipated as heat in the relevant resistors, thus protecting the safe operation of the IGBT.
The resistor and capacitor values in Figure 4(c) are selected based on empirical data: for example, the capacitance of PM200DSA060 is 0.221xF~0.47xF, its withstand voltage is 1.1 to 1.5 times that of the IGBT, and its resistance is 10Ω-20Ω. The resistor power is calculated using P=fCU²xlO⁻⁶, where f is the IGBT operating frequency and u is the IGBT's peak operating voltage. C is the capacitor connected in series with the resistor in the snubber circuit. A fast recovery diode is selected. To ensure the reliability of the snubber circuit, a pre-packaged snubber circuit as shown in Figure 4 can be selected according to the power rating.
Furthermore, the stray inductance of the bus inductance, snubber circuit, and its components has a significant impact on the IPM, especially high-power IPMs, so the smaller the better. Reducing these inductances requires a multi-pronged approach: the DC bus should be as short as possible; the snubber circuit should be placed as close to the module as possible; low-inductance polypropylene non-polar capacitors, fast-speed snubber diodes matched to the IPM, and non-inductive bleeder resistors should be used.
6. Application of IPM in Single-Phase Full-Bridge Inverters
The single-phase full-bridge inverter circuit shown in Figure 5 mainly consists of an inverter circuit and a control circuit. The inverter circuit includes an inverter full-bridge and a filter circuit, where the inverter full-bridge completes the DC-to-AC conversion. The filter circuit filters out harmonic components to obtain the required AC power; the control circuit controls the switching transistors in the inverter bridge and implements some protection functions.
The inverter full-bridge in the diagram consists of four switching transistors and four freewheeling diodes. During operation, the switching transistors switch on and off at high frequencies. At the moment of switching, the voltage and current of the switching transistors increase, resulting in high losses and increased junction temperature. Coupled with parasitic inductance, oscillation, and noise in the power circuit, the switching transistors are very prone to instantaneous damage. In the past, discrete components were commonly used to design the protection and drive circuits for the switching transistors, resulting in a large and unreliable circuit.
The author used a pair of PM200DSA060 dual-unit IPM modules to replace the combinations V1, D1, V2, D2 and V3, D3, V4, D4 in the diagram, respectively, to construct a full-bridge inverter circuit. Utilizing DSP control of the IPM, the design and debugging of a medium-frequency 20kW, 230V inverter were completed. The design employed the drive circuit described above, the buffer circuit shown in Figure 4(c), and a DSP-controlled software IPM protection circuit. Design practice demonstrates that using IPM simplifies system hardware circuitry, shortens system development time, improves reliability, reduces size, and enhances protection capabilities.
