Abstract : With the widespread application of high-voltage frequency converters in industrial fields, users have placed higher demands on the operating performance and product manufacturing processes of the devices. This requires frequency converter manufacturers not only to ensure product quality and operational stability, but also to achieve greater perfection in product manufacturing processes. Improving the manufacturability and aesthetics of the product requires ensuring that the product achieves the same functionality and optimizing the software control method to reduce hardware resource investment. This paper will explain the implementation of pulse signal transmission encoding technology in high-voltage frequency converters through a detailed analysis of pulse signal encoding technology.
Keywords : high-voltage frequency converter; pulse code technology; FPGA
Abstract : With the high-voltage inverter applications in the industrial area of the popularity of users of devices operating performance and product technology to a higher demand. This requires not only the inverter manufacturers to ensure product quality and operational stability, and technological aspects of the product be more perfect. Technology to improve products and ornamental appearance, it should be done to ensure that the functions of the same products, the software control to achieve optimization in order to reduce the hardware resources. This pulse signal through a detailed analysis of coding techniques to illustrate the high-voltage pulse signal transmission encoding converter technology to achieve.
Key words : high-voltage inverter; Pulse Coding; FPGA
1 Introduction
During normal operation of a high-voltage frequency converter, the control system and the controlled device require extensive data exchange via transmission lines. Control signals are typically transmitted via optical fiber to the controlled high-voltage switching devices (such as IGBT drive signals). Since control signals are diverse in type and function, a one-to-one transmission method would require a large amount of optical fiber as the signal transmission medium. This is wasteful of hardware resources and places higher demands on product structure and manufacturing processes. Encoding the signals, using encoding technology to differentiate them into different frequency bands, allows multiple signals to be transmitted through a single optical fiber. This saves hardware resources and reduces production and processing requirements.
2. Basic Working Principle of High Voltage Frequency Converters
Most domestically produced high-voltage frequency converters currently employ a series superposition of power units and a VVVF control method. This method is suitable for most fan and pump loads, and most users in metallurgy, water treatment, and power plants use 6KV or 10KV three-phase AC asynchronous motors. The output voltage of high-voltage frequency converters mainly includes 6KV and 10KV. 6KV converters mostly use a 6-unit series configuration, as shown in Figure 1a). Each of the three phases A, B, and C has 6 power units, with each power unit outputting 577V. The phase voltages UAO = UBO = UCO = 3464V, and the line voltages UAB = UBC = UCA = 6000V. 10KV converters use a 9-unit series configuration, as shown in Figure 1b). Each of the three phases A, B, and C has 9 power units, with each power unit outputting 641V. The phase voltages UAO = UBO = UCO = 5773V, and the line voltages UAB = UBC = UCA = 10000V.
The basic working principle of a high-voltage frequency converter is as follows: the DSP in the control unit generates data through complex data calculations. This data is transmitted to the FPGA via a bus. The FPGA generates control signals through logic and timing operations. After encoding, the signals are converted from electrical signals to optical signals and transmitted to the power unit via optical fiber. The power unit receives the optical signals, performs photoelectric conversion, decodes the signals, and uses these signals as control signals to control the operation of the power unit.
3. Algorithm Implementation of Various Signal Encoding Modules in FPGA
The signal encoding algorithm is primarily implemented using a Field-Programmable Gate Array (FPGA). The DSP generates a series of data through complex calculations, which are then sent to the FPGA. Upon receiving this data, the FPGA performs the corresponding encoding processing. Figure 2 shows the block diagram of the signal encoding algorithm implementation. The DSP used is a TI TMS320F206, and the FPGA used is an Altera EP1C6Q240C8.
3.1 Chip Introduction
The TMS320F206 is a digital signal processing chip from Texas Instruments (TI). It features an improved Harvard architecture (separate program and data buses), a high-performance CPU, and an efficient instruction set. The CPU includes a 32-bit CALU, a 32-bit accumulator, a 16×16-bit parallel multiplier, three shift registers, and eight 16-bit auxiliary registers. Instruction speed can reach 25ns per instruction cycle. Peripheral circuitry includes a software-programmable timer, a software-programmable wait state generator, an on-chip phase-locked loop clock generator, and synchronous and asynchronous serial ports.
The EP1C6Q240C8 is part of Altera's mainstream low-cost FPGA Cyclone series. Cyclone devices are manufactured using a 0.13µm process and contain two phase-locked loops (PLLs), 20 M4K RAM blocks, 5980 logic elements (LEs), a maximum user I/O of 185, and support for a high-speed LVDS interface with a performance of up to 311 Mbit/s.
3.2 Implementation of Signal Priority Selection
Signals sent by the DSP (including clock, enable, read/write, control, detection, address, data, and other signals) are written to the FPGA. The FPGA first performs priority processing on the corresponding signals to ensure that important signals are executed first, so as not to affect the normal operation of the system.
Signal priority selection is primarily implemented through logic circuits, as shown in Figure 3, using a graphical design scheme in Altera's Quartus II software on an FPGA. The input signals include three signals: gcm_1, gcm_2, and gcm_3, and the output signals include three signals: gcm_11, gcm_22, and gcm_33. This logic circuit achieves the following: output signal gcm_11 is satisfied as long as gcm_1 is active high. Output signal gcm_22 is satisfied only if gcm_2 is active high and gcm_1 is low. Output signal gcm_3 is satisfied only if gcm_3 is active high and both gcm_1 and gcm_2 are low. Therefore, the priority is implemented as gcm_1 > gcm_2 > gcm_3.
The simulation waveform for signal priority selection is shown in Figure 4. From the simulation waveform, it can be seen that when the input signal gcm_1 is active high, the output signal gcm_11 immediately becomes high. When the input signal gcm_2 is active high and gcm_1 is low, the output signal gcm_22 immediately becomes high. When the input signal gcm_3 is active high and gcm_1 and gcm_2 are low, the output signal gcm_33 immediately becomes high.
Simulation results confirm that this logic circuit can select signal priorities. For example, in control signals, the stop signal should have a higher priority than the start signal; the system will execute the shutdown function as soon as a stop signal is issued. Start can only be executed when all conditions are met.
3.3 Implementation of Data Signal Frequency Divider
In the FPGA, a graphical design scheme using Altera's Quartus II software is employed, with subroutines written in Verilog HDL. As shown in Figure 5, gcm_fp is the graphical representation of the data signal divider program. The data signal divider input signals include three signals: clock, clear, and enable. The outputs are the data quantity q[5..0] and the pulse signal d.
As shown in Figure 6, the simulation waveform of the data signal frequency divider is obtained using ModelSim software. When the clock signal is 50ns and clr is active low, the output signal d will maintain the ean signal if the ean frequency is less than a certain value. If ean remains high, d will output a pulse signal with a certain frequency variation.
3.4 Implementation of the Delay Filter
The input signals of the delay filter include a clock signal and an enable signal, and the output includes data q[5..0] and a pulse signal d. In the FPGA, a graphical design scheme using Altera's Quartus II software is employed, with subroutines written in Verilog HDL language. Figure 7 shows the graphical representation of the delay filter program, gcm_ys. The delay filter primarily filters out glitches from the control signals to prevent interference signals from affecting system operation.
As shown in Figure 8, the simulation waveform of the delay filter using ModelSim software is as follows: when the clock signal is 50ns and ena is high, the output signal d is filtered before being enabled if ena transitions from low to high. This effectively filters out glitches caused by key presses or system interference, ensuring normal system operation.
3.5 Encoding and Gating and PWM Signal Generation
The PWM output of the high-voltage frequency converter signal encoder is shown in Figure 8. It is designed in an FPGA using the graphical design scheme of Altera's Quartus II software, with subroutines written in Verilog HDL. The input signals in the figure include clock, clear signal, signal 1, and signal 3, and the output signal is pwm01.
Signal 1 is divided into signal 2. When signal 3 is enabled, signal 2 is output synchronously with the clock. Signal 3 is delayed, filtered, and divided again before being output synchronously with the clock. Simultaneously, signal 3 serves as the enable pin for signal 2. This ensures that they are output at different clocks, preventing signal conflicts.
As shown in Figure 9, the simulated waveforms of the encoding gating and PWM signal using ModelSim software reveal that when input signal 3 is valid, the output signal pwm01 is the encoded pulse signal of input signal 3. Similarly, when input signal 1 is valid, the output signal pwm01 is the encoded pulse signal of input signal 1. They are independent in time, differing only in pulse frequency. By performing corresponding decoding at the controlled end, input signals 1 and 3 can be executed.
4. Implementation of Pulse Signal Encoding Technology
The program, written in Verilog HDL and implemented by the FPGA, performs logic operations to encode various signals and ultimately generate PWM signals, which can be transmitted to the controlled object via a single optical fiber. The encoded signals include various control signals such as start, stop, reset, and bypass. If the status information of the controlled object is needed, faults or operational statuses can be transmitted back to the FPGA via another optical fiber. This achieves serial data transmission and reception using only two optical fibers, greatly improving the device's practicality.
The high-voltage frequency converter control system makes full use of the hardware resources of the FPGA (EP1C6Q240C8), greatly simplifying the system circuit. The FPGA receives data sent from the DSP, performs corresponding pulse encoding on the data, and then sends it to the power unit, realizing perfect control of high-voltage high-power switching devices through the low-voltage control system.
5 Conclusion
FPGA and DSP-based control systems possess flexible reprogrammability and online debuggability, along with powerful logic processing, timing control, and data processing capabilities. They undoubtedly have broad market application prospects.
References
[1] Wu Jihua, Wang Cheng, Altera FPGA/CPLD Design, Beijing: Posts & Telecom Press, 2005.7
[2] Yang Geng, Luo Yingli, et al., edited by Chen Boshi, *Electric Machines and Motion Control Systems*, Beijing: Tsinghua University Press, 2006.3
[3] Uwe Meyer-Baese, FPGA Implementation of Digital Signal Processing (2nd Edition), translated by Liu Ling, Beijing: Tsinghua University Press, June 2006.
