introduction
In recent years, power electronics technology has developed rapidly, and power electronic control devices have been widely used in various fields. Examples include uninterruptible power supplies (UPS), switching power supplies, locomotive auxiliary power supplies, battery charging and discharging, electronic analog loads, electric locomotives, and electric-drive diesel locomotives. Furthermore, in some countries, such as Denmark, Germany, and the United States, power electronically controlled grid-connected inverters have been gradually applied to the connection of solar power generation and wind power generation devices with the power system.
To keep pace with the rapid development of power electronics technology and improve the modularity of power electronics hardware development, thereby shortening development time, this paper designs and develops a DSP56F803 general-purpose board as a hardware development platform for various power electronics applications. Furthermore, complex programmable logic devices (CPLDs) offer strong programmability and application flexibility, significantly reducing system development costs and shortening development cycles. To enhance the application flexibility of this general-purpose board, this paper utilizes Xilinx's high-performance, low-voltage CPLD XC95XL144 to implement various protection logics and expand four sets of input/output ports. The integrated application of the DSP56F803 and XC95XL144, serving as the core of the general-purpose board, is a key feature of this design.
1 Design Concept
The main principle followed in designing this general-purpose board is to improve anti-interference capability and application flexibility while meeting as many functional requirements as possible. This can significantly reduce the hardware development cost of power electronics applications, shorten development time, and improve application stability. The general-purpose board designed in this paper uses DSP and CPLD as its core components and develops a rich and flexible set of peripheral circuits. First, this paper uses Xilinx Foundation 3.li software and VHDL hardware description language for simulation and synthesis. Finally, this paper uses Xlinx's XC95XL144 high-performance programmable logic device (CPLD) to implement various protection logic and expand four sets of input/output ports.
When designing a general-purpose DSP board, the first consideration should be the functional modules that can be expanded.
1. Pulse width modulation (PWM) technology has been widely used in various power electronic control applications, therefore, the output of the PWM module was expanded first. The frequency and duty cycle of the PWM in the DSP56800 series can be continuously varied, thus enabling stepless frequency conversion speed regulation.
2. Power electronic control inevitably requires sampling various voltage and current signals. Therefore, this paper extends the DSP's 8-channel 12-bit analog-to-digital converter (ADC).
3. Currently, most power electronic control systems require communication between DSPs or between DSPs and PCs. Therefore, this paper extends the asynchronous serial communication module SCI. In order to improve anti-interference capability, increase transmission distance, and realize remote monitoring, this paper adopts RS-485 differential communication.
4. More and more power electronic devices are operating in grid-connected mode, so it is necessary to detect the zero-crossing point and period of the power grid. This paper extends the timer module TIMER, whose interface can be used for the detection of the zero-crossing point and period of various signals.
5. Power electronics applications generally only need to record a small amount of fault data. Therefore, this paper only expands the 64K ferroelectric non-volatile memory FM24CL64, which only requires two wires for reading and writing, and there is no delay in reading and writing.
6. Most systems have a clock to record the time of a fault, which is used for fault data analysis. This article extends the real-time clock X1226, which shares clock lines and read/write signal lines with the FM24CL64, only the physical addresses of the two devices are different.
7. Finally, this article also expands on the power monitoring and hardware watchdog chip MAX706RESA.
The interface between DSP56F803 and XC95XL144 mainly includes the protection function of overvoltage and overcurrent protection signals detected by the power electronic main circuit, which are triggered by the CPLD logic operation to achieve the protection function of DSP external interrupt or PWM error protection pin PWMFAULT; and the use of low address lines and low data lines to expand input and output ports.
The subroutines for the DSP56F803 peripheral modules are written using the Embedded SDK, as it provides drivers and interfaces for various peripheral modules, making it easy to use even without familiarity with the DSP's internal hardware structure. For read/write operations between the DSP56F803 and the XC95XL144, this paper develops its own SDK package based on the DSP56800 series assembly instruction set.
2 Hardware Design
The anti-interference design of printed circuit boards (PCBs) is closely related to the specific circuit. This paper fully considers the requirements of anti-interference design when designing the hardware of a general-purpose board. To improve the stability and anti-interference capability of the general-purpose board, a high-speed four-layer board is designed, with the middle two layers for power and ground respectively, and the top and bottom surfaces for signal lines. To improve the anti-interference capability of power and ground, ferrite beads are used to connect digital and analog power supplies, as well as digital and analog grounds. Capacitors are connected between analog grounds and analog power supplies, and between digital grounds and digital power supplies. To eliminate common impedance coupling, decoupling capacitors of appropriate capacitance are configured at critical parts of each chip.
Figure 1: Hardware Structure Diagram of DSP General Version
2.1 Introduction to Core Chips
This paper uses the DSP56F803 from the DSP56800 series of digital signal processors. The DSP56800 series employs a Harvard architecture, separating the program space and address space. This allows for parallel fetching of the next instruction from the program space while processing data operations and data transfers, improving processing speed. The DSP56800 series digital signal processors feature abundant I/O ports and a variety of peripheral devices. The DSP chip integrates general-purpose input/output (GPIO), asynchronous serial communication (SCI), pulse width modulation (PWM), analog-to-digital converter (ADC), synchronous serial communication (SSI), CAN2.0A/B (control LAN), timers, and other peripheral modules, achieving complete monolithic design.
The XC95XL144 is a high-performance, low-voltage programmable logic device from Xilinx. It has 100 pins, integrates 3200 typical available gates, 144 logic cells, and 74 available I/O ports, which can be individually configured for input, output, and bidirectional operation. It features three global clocks, three global enable pins, and one global clear pin. It supports 3.3V and 2.5V operation with a propagation delay of only 5 ns. Furthermore, the XC95XL144 supports in-system programming, with programs downloaded via the JTAG interface, making it simple and convenient to use.
2.2 Design of Main Functional Modules of DSP56F803 General-Purpose Board
2.2.1 Pulse Width Modulation Module (PWM)
The PWM module is primarily used for controlling the switching devices in power electronic converters and various motor controls. The module has six output channels, which can be configured in software as follows: 3 complementary pairs; 2 complementary pairs and 2 independent channels; 1 complementary pair and 4 independent channels; or 6 independent channels. In complementary operation mode, programmable dead time insertion is allowed to prevent through-short circuits between the upper and lower bridge arms. The PWM frequency and duty cycle are continuously adjustable. Stepless frequency conversion can be achieved through output waveform distortion correction by a current sensor and independent polarity control of the top and bottom output pins.
2.2.2 Analog-to-Digital Conversion Module (ADC)
An ADC can be used to sample various signals such as current, voltage, and speed. An ADC includes eight input channels and two independent sample-and-hold circuits, with a conversion accuracy of 12 bits. The conversion process can be triggered by a synchronization signal or by writing to the START bit of the control register. Input modes can be either single-sided or differential.
2.2.3 Serial Communication Module (SCI)
SCI is a full-duplex asynchronous communication interface that uses the standard non-return-to-zero (NRZ) data format. It allows programmable selection of 8-bit or 9-bit data formats and features independent SCI transmitters, receivers, and interrupt requests. While most PCs use RS-232 interfaces, their transmission distance is only about 50 feet. The general-purpose board uses RS-485 differential communication, improving interference immunity and achieving a maximum transmission distance of over 4000 feet, suitable for remote monitoring. This allows PCs or other DSP boards to communicate with the general-purpose board via isolated RS-485 communication.
2.2.4 Timer Module
The timer has two main functions: to trigger specific events at regular intervals; and to record the number of internal clock cycles elapsed between two external events, thus obtaining the time period of the external events. Therefore, the interface can be used for zero-crossing detection of various signals. When used with various grid-connected devices, it can detect the zero-crossing points and cycles of the power grid.
2.2.5 Since power electronics generally only require fault data, this paper does not expand the memory via the bus.
A 64K ferroelectric non-volatile memory, the FM24CL64, was expanded using only two general-purpose input/output ports. The FM24CL64 is an 8192x8-bit structure, allowing for continuous and random read/write operations with no latency. It utilizes highly reliable ferroelectric materials and offers a storage life of up to 45 years. This paper also expands upon the X1226 real-time clock, recording the time of fault occurrence along with fault data for analysis. The X1226 features two alarms and a 512-byte electrically erasable read-only register, integrated crystal oscillator compensation circuitry, and battery backup. It can be programmed to control the output of alarm signals from the PHZ/IRQ pins or three different frequency signals related to the clock frequency.
2.2.6 To prevent low power supply voltage, this paper uses a power supply voltage monitoring chip.
Its detection circuit sends a reset signal to reset the entire system when the power is on and when the power supply voltage is low. It also has a watchdog timer function. If the WDI pin level of the DSP does not toggle within 1.6 seconds, it will send a reliable reset signal to the DSP, which enhances the anti-interference capability.
2.3 Design of the interface between DSP56F803 and XC95XL144
The main principle followed when arranging the pins of the XC95XL144 in this article is to place input/output ports with similar electrical characteristics in the same macrocell as much as possible, and the arrangement order is based on the principle of convenient wiring. The interface between the general-purpose DSP56F803 and the XC95XL144 includes: data select line DS, low-order data lines D0-D7, low-order address lines A0-A3, and A6 as the reset control terminal of the XC95XL144, six PWM output signals, and three error protection pins PWMFAULTA0-PWMFAULTA2, as well as external interrupts IRQA and IRQB. This article only introduces the general functions of the XC95XL144; other specific functions need to be modified according to the specific power electronics application requirements of the VHDL language program.
The DSP56F803's address line A6 is configured as a general-purpose input/output port, serving as the reset control RESET for the XC95XL144. When RESET is low, the XC95XL144 is reset, and the output port is set to low (active high). The DSP56F803's six PWM outputs are connected to the XC95XL144 as inputs, corresponding to six output ports. These can be logically manipulated before output, thus expanding its application to a wider range of control scenarios. Overvoltage and overcurrent signals from the power electronic main circuit are input to the CPLD, processed through specific logic, and trigger the DSP's external interrupts IRQA and IRQB or the PWM error protection pin PWMFAULT to achieve protection functions. The DSP56F803's data select line DS is connected to the XC95XL144, working in conjunction with the low-order address lines to control the read/write operations of four groups of eight input/output ports each. Since the specific input/output ports are usually determined, this design, to improve stability, specifies two groups of input ports and two groups of output ports.
3 Software Design
For the DSP56800 series products, Motorola provides two software development tools: one is the Codewarrior integrated development environment, a reliable development tool for cross-assembly, cross-C compilation, linking, and debugging. Metrowerks, a subsidiary of Motorola, includes a visual project creation and management system in its Codewarrior integrated development environment, providing comprehensive management of source code files and libraries, reducing project complexity. The other is the Embedded SDK software development tool, which is not essential for DSP development, but it can greatly reduce the difficulty of development work and speed up the development process. Writing subroutines for the various modules of DSP peripherals is easy to master using the Embedded SDK, so it will not be described in detail here.
For CPLDs, this paper first uses Xilinx Foundation3.li software for compilation and simulation. The source code for controlling the two sets of input and output ports through low-order address selection and low-order data lines is as follows:
PROCESS(RD,RESET) // Read process BEGIN
IF(RESET='1')THEN //Reset signal internal_bus_in<="ZZZZZZZZ";//Internal bus signal ELSIF(RD='0')THEN
IF(A0='0' AND A1='0')THEN // Address selection internal_bus_in<=IOA;
ELSIF(A1='0' AND A0='1')THEN
internal_bus_in <= IOB;
END IF;
ELSE
internal_bus_in<="ZZZZZZZZ";
END IF;
D<=internal_bus_in;
END PROCESS;
PROCESS(WRR, RESET) // Write process BEGIN
IF(RESET='1') THEN
IOC<="00000000";
IOD<="00000000";
ELSIF(WR'EVENT AND WR='1') THEN
IF( A0='0' AND A1='0') THEN
IOC <= D;
ELSIF(A1='0' AND A0='1') THEN
IOD <= D;
END IF;
END IF;
END PROCESS;
When performing integrated debugging of DSP and CPLD, this paper develops an SDK software package for CPLD I/O read and write operations based on the DSP56F803's read and write operations to the XC95XL144's input/output ports, which is based on the DSP56800 series assembly instruction set. Reading and writing the corresponding I/O ports only requires a simple call to the software package program.
4. Conclusion
This paper designs a general-purpose DSP board based on a power electronics application platform. The various peripheral expansion modules of the DSP have been completed and debugged using the DSP56800's Embedded SDK software development tool through the writing of some small programs. After successful simulation with Xilinx Foundation 3.li software on the XC95XL144, comprehensive testing was conducted, followed by programming the chip for further experiments. Based on actual operating conditions, the program was improved. The author's innovation lies in developing an SDK software package for DSP to read and write four sets of CPLD I/O ports and completing the comprehensive debugging of the DSP and CPLD, thus improving the flexibility of the general-purpose board.
