1 Introduction
In recent years, with the continuous development of power electronic devices, the application of high-voltage static var compensators (SVCs) has become increasingly widespread, especially in important applications such as metallurgy, mining, and electrified railways, where TCR devices play a crucial role. For the control process of high-voltage reactive power compensation controllers, rapid real-time data processing is essential. It requires transmitting constantly changing data from the field to the controller in the shortest possible time for processing and ultimately controlling the entire system. Traditional high-voltage reactive power compensation equipment typically uses a single DSP along with memory, an analog-to-digital converter (ADC), and peripheral interfaces to form a complete control system. However, this approach is not feasible for achieving high-speed real-time control. A real-time control system generally needs to perform tasks such as data acquisition, analog-to-digital conversion, analysis and calculation, digital-to-analog conversion, real-time process control, human-machine interface, and communication with external systems. Relying solely on a single DSP to perform these tasks would significantly extend the system's control cycle, reduce control accuracy, and thus affect the overall system performance. A dual-CPU approach can solve this problem, where two CPUs form a master-slave system to complete the corresponding functions. The key to master-slave system design is achieving high-speed data communication between the master and slave CPUs. Generally, there are four main methods for data communication between master and slave: serial, parallel, DMA, and dual-port RAM. Considering the advantages and disadvantages of various communication methods, and taking into account the high real-time performance and high control precision of the TCR system, the dual-port RAM device CY7C133 was used as the shared memory to complete the TCR data communication system design, realizing high-speed data communication between the master and slave CPUs of the TCR system.
2TCR Data Communication System Composition Structure
The block diagram of the TCR data communication system is shown in Figure 1. The system uses the TI TMS320F2812 DSP chip and the Intel 80C196 16-bit microcontroller as the CPU of the control system. Data exchange between the two CPUs is completed through the dual-port RAM CY7C133.
The main function of the TCR data communication system is to receive control commands and setting parameters written to the dual-port RAM by the CPU (INTEL80C196), and transmit these commands and parameters to the DSP. Upon receiving these instructions, the DSP either sets a data range or implements corresponding control strategies, and controls the system to make appropriate adjustments. After the system stabilizes, the DSP writes some important real-time data into the dual-port RAM, which is then retrieved by the CPU. The CPU can then transmit the data from the dual-port RAM to a host computer for real-time monitoring and processing. Using dual-port RAM is an effective way to solve data sharing between CPUs. Compared with traditional serial communication, dual-port RAM not only offers higher data transmission speeds but also better anti-interference performance.
The DSP chip used in this system is the new generation TMS320F2812 from TI, featuring a 32-bit data bus, a 24-bit address bus, and a speed boost to 150MHz. It integrates 18K×16-bit SRAM, 128K×16-bit FLASH, 4K×16-bit BootROM, and 1K×16-bit OTPROM. It also boasts a rich set of peripherals, including a 2×8-channel, 12-bit, 80ns conversion time, 0-3V range ADC, a CAN bus transceiver, and 12-channel PWM outputs. The other CPU circuit is the Intel 80C196, a 16-bit microcontroller from Intel, featuring an internal 8-channel 10-bit high-speed A/D converter and PWM outputs, making it a high-performance microcontroller. The dual-port RAM uses the CY7C133 chip manufactured by Cypress. This chip is a high-speed 2K×16 CMOS dual-port static RAM with two independent and completely symmetrical address, data, and control buses. It is packaged in a 68-pin PLCC and has a maximum access time of 25/35/55ns. The CY7C133 allows two CPUs to read any memory cell simultaneously (including reading the same address cell simultaneously), but does not allow simultaneous writing or a read-write operation on the same address cell; otherwise, an error will occur. An arbitration logic (busy logic) circuit is introduced in the dual-port RAM to solve this problem: when the left and right ports simultaneously write to or read from the same address cell, the port whose address is stabilized first prioritizes the read/write operation through the arbitration logic circuit. Simultaneously, the internal circuitry enables the signal of the other port and internally prohibits access from the other port until the operation on the current port is complete. Since the TMS320F2812 has a 32-bit data bus width, while the CY7C133 has a 16-bit data bus width, the lower 16 bits of the TMS320F2812 data bus are connected to the dual-port RAM's data bus.
Figure 1 Block diagram of TCR data communication system
3TCR Data Communication System Design
3.1 Working process of TCR data communication system
First, the CPU sends data to the data bus of the dual-port RAM. If the DSP is not writing data to the same cell in the dual-port RAM at this time, the CPU's data can be written to the dual-port RAM. If the DSP reads data from that cell, it can retrieve the data and perform corresponding processing. After the system responds to these processing and adjusts the output, the DSP obtains the latest real-time data of the system and sends it to the data bus of the dual-port RAM. If the CPU is not writing to the dual-port RAM at this time, the DSP's data can be written to the dual-port RAM. Similarly, the CPU can immediately read the data and use it for real-time monitoring and display.
3.2 Hardware Design of TCR Data Communication System
Figure 2 shows the circuit connection diagram of the TCR data communication system. Since the internal structure of the dual-port RAM (CY7C133) is a dual-port memory array, the left and right ports can share the memory array and each has its own control lines. When accessing data individually, it behaves the same as ordinary RAM. Simultaneous reading of data from different memory spaces and reading of data from the same memory space can be performed by both the DSP and CPU. When the CPU reads data from the dual-port RAM, it first sets the CPU's chip select signal /CER to an active level, then sets the dual-port RAM's read enable signal /OER to a low level, and then sends the corresponding address to the A0R-A10R address bus. The 16 bits of data stored at that address in the dual-port RAM are then read and sent to the 80C196 via the D0R-D15R data bus. When the CPU performs a write operation on the dual-port RAM, it also needs to set the CPU's chip select signal /CER to an active level, then set the dual-port RAM's control signal /OER to a high level, and finally send the data to the address corresponding to the A0R-A10R address bus via the D0R-D15R data bus. When the DSP reads data from the dual-port RAM, the method is the same as described above, except that the DSP's chip select signal becomes /CEL, the control signal becomes /OEL, the address lines become A0-A10, and the data lines become D0-D15. However, if write operations are performed on the same data space simultaneously, or if one port performs a read operation on one data space while another port performs a write operation on the same data space, a conflict will occur between the CPU port and the DSP port. The CY7C133 handles these two situations through the BUSY pin. When the CPU port and DSP port perform read and write operations on different memory spaces, they can access the data simultaneously. At this time, the BUSY signals of both the CPU port and the DSP port are set high simultaneously. If a storage operation is performed on the same memory space simultaneously, the BUSY signal of the port that receives the storage request signal first is set high, allowing storage. The BUSY signal of the port that receives the storage request signal later is set low, disallowing storage. It is important to note that the time difference between the two access request signals must be greater than 5ns; otherwise, the arbitration logic cannot determine which access request signal came first. If the time difference between the two access request signals is less than 5ns, the arbitration logic sets the BUSY signal of one port high and the BUSY signal of the other low, thus ensuring that one port performs data storage while the other port performs data reading, avoiding conflict.
Figure 2. Circuit connection diagram of TCR data communication system
3.3 TCR Data Communication System Software Design
Dual-port RAM requires a mechanism to coordinate read and write operations between the CPU and DSP; otherwise, data errors will occur. Here, the storage space of the dual-port RAM can be divided into odd and even address spaces. The odd address space is dedicated to writing to the 80C196, and the even address space is dedicated to reading from the 80C196. Therefore, we only need to process the TMS320F2812 software accordingly. That is, the TMS320F2812 only reads from the odd address space of the dual-port RAM and only writes to the even address space. This avoids write operations to the same address unit of the dual-port RAM by both the TMS320F2812 and the 80C196. Furthermore, before accessing the dual-port RAM, the CPU or DSP first checks the local /BUSY signal. Read and write operations are only performed if the local /BUSY signal is invalid, further ensuring the reliability of data read and write operations.
4. Conclusion
This paper introduces a high-speed data communication system applied to TCR devices. This system solves the problems of long data transmission time, slow processing speed, complex structure, and impact on the overall system performance of previous data communication devices. It provides a practical and efficient system design method for achieving high-speed communication between the CPU and DSP. This method not only simplifies the system's hardware configuration and software programming but also enables the system to achieve high communication speed, ensuring real-time performance and reliability. Furthermore, the interface circuit designed between the CPU/DSP and the dual-port RAM in the system features simple and practical logic control and good portability to other application systems.
References:
[1] Wan Shanming. TMS320F281xDSP Principles and Application Examples, Beijing University of Aeronautics and Astronautics Press, 2007.
[2] Sun Hanfang. Intel 16-bit Microcontroller 1999
[3] Li Xiaoqing. Application of Dual-Port RAM in Multi-CPU Computer Measurement and Control Systems. Microcomputer Information, 1999.
[4]Cypress Semiconductor Corporation． CYPRESSPRODUCTSDATABOOK
About the author:
Wang Guoqiang (1979-) Male Engineer/Master of Engineering Research direction: control system of high voltage frequency converter and high voltage reactive power compensation device.
Current position: Power Grid Division, Harbin Jiuzhou Electric Co., Ltd.
Mailing address:
No. 162, Haping Road, Nangang District, Harbin City, Heilongjiang Province
Harbin Jiuzhou Electric Co., Ltd. Power Grid Division
Postal code 150081
Telephone: 13936307357
drive--5.30
