Abstract: For grid-connected wind power converters, accurately and quickly obtaining the phase angle of the three-phase grid voltage is crucial for successful grid connection. This paper analyzes various phase-locked loop (PLL) technologies and ultimately adopts a software PLL to achieve grid connection of the converter. Furthermore, the details of the software PLL technology are optimized to ensure the safe and reliable grid connection of the wind power converter system.
Keywords: direct-drive wind power converter, SPLL, Z-transform
GRID-SIDECONVERTERSPLLINDIRECTDRIVEWINDPOWERSYSTEM
1 Introduction
In the grid connection process of permanent magnet direct-drive wind power converters, accurately and quickly obtaining the phase angle of the three-phase grid voltage is a prerequisite for ensuring good steady-state and dynamic performance of the entire system. Phase-locked loops (PLLs) are generally used to obtain the grid voltage phase; therefore, high-performance PLLs must be designed.
2 phase-locked loops
2.1 Overview and basic structure of phase-locked loops [1,2]
The general approach to obtaining the phase angle of the grid voltage is to first generate a signal synchronized with the grid voltage, and then obtain the phase angle through the synchronization signal. There are many methods to generate a synchronization signal; the simplest is to use the grid voltage as the synchronization signal. However, this method is not suitable because the grid voltage waveform distortion can lead to distortion of the system's output voltage and current, and even affect system stability. A phase-locked loop (PLL) is generally used to obtain the phase angle of the grid voltage. A PLL typically consists of a phase detector, a loop filter, a voltage-controlled oscillator (VCO), and a frequency divider, as shown in Figure 2-1. Its basic working principle is that the phase detector converts the phase difference between the grid voltage and the internal synchronization signal of the control system into a voltage. After filtering by the loop filter, this voltage is used to control the VCO, thereby changing the frequency and phase of the internal synchronization signal to match the grid voltage.
Figure 2-1 Basic structure of a phase-locked loop
2.2 Classification of Phase-Locked Loops
Phase-locked loop (PLL) is an automatic control system that synchronizes the phases of two electrical signals. It's also known as automatic phase control technology. The negative feedback loop structure ensures that the output signal is phase-synchronized with the reference signal. PLLs are widely used in communications, radio, and power system automation to perform signal processing, modulation and demodulation, clock synchronization, frequency multiplication, and frequency synthesis.
Phase-locked loops (PLLs) can be categorized into analog PLLs (APLLs), mixed-signal PLLs (Mixed-Signal PLLs), digital PLLs (DPLLs), and software PLLs (SPLLs). Analog PLLs are a mature technology, and their unique and superior performance has led to their widespread application in many fields. In recent years, with the development of digital technology, the fully digital control of inverter power supplies has become an inevitable trend, thus PLLs are gradually transitioning to digital control. Software PLLs are easier to implement and port compared to analog PLLs, and replacing hardware with software also saves costs. The system described in this paper utilizes software PLL technology.
2.3 Basic Structure of a Three-Phase Software Phase-Locked Loop
For a three-phase power grid, it is difficult to accurately synchronize the dq coordinate system with the three-phase voltage composite vector of the power grid using the single-phase synchronization method. It is necessary to integrate the phase information of the three-phase voltage. As shown in Figure 2-2, when the magnitude of the power grid voltage, i.e. the magnitude of the voltage composite vector Us, remains unchanged, the q-axis component Usq of Us reflects the phase relationship between the d-axis and the power grid voltage Us. When Usq>0, the d-axis lags behind Us, and the synchronization signal frequency should be increased; when Usq<0, the d-axis leads Us, and the synchronization signal frequency should be decreased; when Usq=0, the d-axis is in phase with Us. Therefore, the in-phase relationship between the two can be achieved by controlling Usq to make Usq=0. Based on this idea, a three-phase software phase-locked loop (SPLL) implemented by DSP was designed. Each inverter unit has a phase-locked loop in its parallel controller and single-machine controller, which are all implemented in software in this system. [3]
Figure 2-2 Voltage Vector Phase Diagram Figure 2-3 Block Diagram of Three-Phase Software Phase-Locked Loop
As shown in Figure 2-3, the grid voltage is transformed into Usq[4], and after passing through a loop filter, the oscillation frequency of the voltage-controlled oscillator is changed. When implemented with a DSP, the cyclic counting of the DSP's internal timer is generally used to generate a synchronization signal and realize the functions of the voltage-controlled oscillator and frequency divider. Therefore, the frequency and phase of the synchronization signal can be changed by changing the period of the timer or the maximum cyclic count value.
2.4 Mathematical Model of Three-Phase Software Phase-Locked Loop
Since the phase-locked loop is implemented in software in this system, we will first analyze the phase-locked loop implementation method in the digital domain, and then derive the z-domain mathematical model of the phase-locked loop.
Figure 2-4 Schematic diagram of output voltage leading synchronization signal SYN
Figure 2-6: Control block diagram of closed-loop phase-locked loop
3. Error and accuracy of three-phase software phase-locked loop
3.1 Error Analysis of Three-Phase Software Phase-Locked Loop
Steady-state error of a control system is a measure of the system's control accuracy (control precision), often referred to as steady-state performance. In control system design, steady-state error is a crucial technical indicator. For a control system corresponding to a given time base, due to differences in system structure, the type of input (control variable or disturbance variable), and the form of the input function (step, ramp, or acceleration), the steady-state output of the control system cannot be known or equivalent to the input variable under both human and natural conditions, nor can it accurately recover to the original equilibrium position under any form of disturbance. It can be said that steady-state error in a control system is unavoidable. One of the tasks of control system design is to minimize the system's steady-state error, or to make the steady-state error less than a certain allowable value. The stability conditions of the system have been discussed above; discussing steady-state error is only meaningful when the system is stable.
From Figure 2-6, the system error transfer function under the input signal is obtained as follows:
3.2 SPWM remodulation technique for improving phase-locked loop accuracy
Phase-locked loop (PLL) accuracy is a critical issue in PLL technology, directly impacting the reliability of parallel inverter connections. The PLL accuracy of the inverter output voltage is related not only to the accuracy of phase error detection and controller performance but also to the accuracy of the inverter output cycle control. To address the issue of low PLL accuracy caused by microprocessor clock and switching cycles, this literature proposes SPWM remodulation technology, which can effectively improve the PLL accuracy of the inverter output voltage.
The so-called "SPWM remodulation control" refers to a method that, based on the original SPWM modulation, selects a portion of the carrier waves as remodulation units according to a certain strategy, and superimposes the clock control periods that need to be compensated onto the period counters of these carrier waves to improve phase control resolution and achieve high-precision synchronous control. Commonly used remodulation control strategies in practical digital control systems include sequential interpolation, grouped sequential interpolation, and symmetrical interpolation. This paper adopts segmented sequential interpolation technology, achieving precise phase control through precise control of the carrier period. Taking a DSP as the main controller as an example, when using SPWM technology, the carrier ratio at a certain switching frequency is N. When generating the carrier using a continuous increment/decrement counting mode, the theoretical minimum phase-locked accuracy is 2N times the counting time base. If a segmented sequential interpolation technique is used to compensate for the carrier period, dividing N into n segments, and performing periodic sequential interpolation compensation on the carrier period in each segment as needed, and using the same continuous increment/decrement counting mode to generate the carrier, assuming the counting time base remains unchanged, the theoretical minimum phase-locked accuracy is 2n times the counting clock. Compared to not using interpolation technology, the phase accuracy is increased to N/n times the original.
This technique of using segmented sequential interpolation to compensate for the carrier period enables more precise control of the carrier period and effectively improves the phase-locked loop's (PLL) phase-locking accuracy.
4. Experimental Results and Analysis
The software phase-locked loop designed in this paper is based on a permanent magnet direct-drive wind power converter system. As shown in Figure 4-1, this converter is a 1.5MW rated power direct-drive wind power converter prototype, which has been debugged and tested. The converter adopts a PWM back-to-back topology, using two PWM rectifiers in parallel on the motor side and the grid side, sharing a DC bus between the rectifier and inverter. This shared bus structure increases the power rating but also introduces circulating current, making system control more complex than a single module. Appropriate reactors are used for filtering on the grid side of the converter to improve power quality.
Figure 4-1 Experimental platform for grid-side converter of permanent magnet direct-drive wind power system
During debugging, only the main functional components of the prototype were tested and experimented on, and the tracking performance of the phase-locked loop was tested based on this. The main experimental parameters were: IGBT switching frequency of 1.5 kHz, modulation frequency fr = 50 Hz, DC bus voltage Udc = 1100 V, rated power of 1.5MW, grid-side rated voltage of 690V, and rated current of 1255A, etc.
Figure 4-2 Grid-connected phase-locked loop process
Figure 4-2 shows the waveform of the grid-connected current tracking the grid voltage phase under the action of the phase-locked loop (CH1 is the grid voltage waveform, CH2 is the grid-connected voltage signal). Since the program uses a table reading method, there will be a certain phase error. The theoretical maximum phase error is 2π/2¹⁶ = 9.6 × 10⁻⁵ (rad), which is quite small and meets the design requirements. As can be seen from Figure 4-2, the phase difference between the two signal waveforms gradually decreases during the grid-connected current tracking the grid voltage, and the steady-state error has met the requirements for practical applications. From the prototype test of the direct-drive converter, the accuracy and speed of the phase tracking of the soft phase-locked loop module meet the design standards for practical applications.
4 Conclusion
A digital soft phase-locked loop (PLL) technology was used to achieve phase-locking in a wind power grid-connected system. Prototype tests showed that this PLL system has advantages such as high accuracy, stability, speed, and ease of implementation, and can well meet the grid connection requirements of wind power systems. It also has certain reference value for other converter systems.
