Development of a DSP-based Image Data Processing System for Empty Beer Bottles

1 Introduction

Machine vision systems for empty bottle inspection machines come in three architectures: PC-based, DSP-based, and smart camera-based. Regardless of the architecture, the imaging system uses a high-speed industrial camera and optical illumination system to clearly image the object being inspected, followed by subsequent image conversion and processing. Embedded systems based on smart cameras complete image acquisition, transmission, and processing within the smart camera itself, offering high system integration and fast processing speed, but also requiring specialized expertise and a long development cycle. Currently, the first two methods are primarily used.

The processing of images of the bottle opening and bottom involved algorithms such as low-pass filtering and edge extraction. These convolution algorithms require numerous multiplication and addition operations and demand high image processing speed. Considering the processor speed and on-chip peripheral requirements, the processor on the board is the Texas Instruments (TI) TMS320VC5502 high-performance digital signal processor.

This article first introduces the features of the VC5502DSP, then introduces peripheral interfaces such as system clock, extended memory interface, and serial communication interface, elaborates on the boot mode and target program memory space addressing, and finally gives the timing sequence for burning extended program memory.

2. Introduction to VC5502DSP

2.1 Features of TMS320VC5502

The TMS320VC5502 is a fixed-point DSP with the following main features:

Based on the high-performance, low-power TMS320C55x CPU core. 3-/5-ns instruction cycle, 300/200MHz clock rate; 16KB instruction cache; 600/400 mega-accumulator operations per second (MMACS).

The internal bus architecture includes one internal program bus, three internal data read buses, and two internal data write buses. Without external bus contention, three data reads and two data writes can be performed within one clock cycle, demonstrating a high degree of parallelism.

Two 40-bit multiply-accumulate units (MACs), each capable of performing a 17-bit × 17-bit operation within one clock cycle, supplemented by a 40-bit arithmetic logic unit (ALU) and a 16-bit arithmetic logic unit.

Variable-length instructions increase instruction density, with the Instruction Unit (IU) fetching 32 bits of instruction at a time and queuing them in the Program Unit (PU). The PU decodes the instructions, executes them, allocates tasks to the Address Unit (AU) and Data Unit (DU), and maintains a fully protected instruction pipeline. Branch prediction techniques reduce pipeline flushing caused by conditional instructions.

The EMIF interface provides seamless connectivity to asynchronous EPROM, SRAM, SDRAM, and asynchronous burst SRAM (SBSRAM). Program memory and data memory are uniformly addressed, supporting an 8MB 16-bit memory space divided into four regions (CE).

In addition, TI provides a range of development tools and packages, including eXpressDSP, CodeComposerStudio, DSP/BIOS, TI standard algorithm libraries, signal processing algorithm libraries, video and image processing algorithm libraries, etc., which improve users' development efficiency.

2.2 System Clock Settings

The TMS320VC5502 can use an external crystal oscillator and an internal oscillator as clock sources, or it can directly use an external clock source. The VC5502 has an internal phase-locked loop (PLL), which can be enabled or bypassed; the PLL is bypassed by default during power-on reset. The DSP's clock source is determined by the state of the GPIO4 pin during reset.

The TMS320VC5502 is divided into four clock groups: the C55x core system clock group, the fast peripheral clock group, the slow peripheral clock group, and the EMIF interface clock group, corresponding to the four internal clock signals CLKOUT3, SYSCLK1, SYSCLK2, and SYSCLK3, respectively. The fast peripheral clock SYSCLK1 is mainly used by the DMA and HPI interfaces, the slow peripheral clock SYSCLK2 is mainly used by the I2C module in this application, and the EMIF interface clock SYSCLK3 is used as the memory access clock.

In this image processing card, the MK1711 with a frequency of 200MHz is used as the external clock source. The MK1711 is the DSP external clock recommended by Texas Instruments. The GPIO4 pin is connected to a high level during reset, and its state is detected by the bootloader, which sets CLKMD[0] to 1.

When the EMIF module uses the internal clock as its clock source, the frequency of SYSCLK3 must be less than or equal to 100MHz; when the EMIF module uses an external clock source, the frequency of SYSCLK3 must be less than or equal to SYSCLK1, but the frequency of the external clock source CLKIN must be less than 100MHz. The frequency of SYSCLK2 must be less than or equal to the frequency of SYSCLK1.

In this application, the frequencies of the various clocks used by the system during normal operation are shown in Table 1 below:

Modifying the C55x subsystem clock control register (PLLCSR), PLL divider register (PLLDIV0), and PLL multiplier (PLLM) requires following a specific order. The modifications for this system are as follows:

1) Clear the PLLEN bit of PLLCSR to put the PLL in bypass mode;

2) Set the PLLRST bit of PLLCSR to reset the PLL;

3) Clear the D0EN bit of PLLDIV0 to disable the PLL divider;

4) Modify the divider value of the PLLDIV0 register to 100b;

5) Set the PLLEN bit of PLLDIV0 to enable the PLL divider;

6) Modify the multiplier value of the PLLM register to 100b;

7) Delay 1 microsecond (still calculated at the original frequency);

8) Clear the PLLRST bit of the PLLCSR to remove the phase-locked loop from the reset state;

9) Poll the LOCK bit of the PLLCSR until the bit is 1, indicating that the phase-locked loop is successful and has a stable frequency output;

10) Set the PLLEN bit of the PLLCSR to 1 to enable the system to enter the phase-locked loop (PLL) enabled mode.

By default, the division factor for the three clocks in SYSCLKx is 4. To speed up peripheral access, this needs to be modified. When modifying the corresponding PLLDIVx registers, TI recommends first putting the corresponding interface into IDLE state to avoid peripheral access errors.

By modifying PLLDIV1=2, the SYSCLK1 clock frequency is set to run at 100MHz; PLLDIV2 is left unchanged with the default value of 4, and SYSCLK2 runs at 50MHz; by modifying PLLDIV3=2, the EMIF interface clock SYSCLK3 runs at 100MHz.

The ECLKOUTx clocks are only required when using synchronous dynamic memory and synchronous burst SRAM, and not when using asynchronous SRAM. To reduce electromagnetic interference, these two clock pins can be disabled by setting EKxEN and EKxHZ of the EMIF global control register EMIFGCRx to 0.

To expedite the boot loading process, the phase-locked loop (PLL) and the clock divider registers for each peripheral can be modified by the bootloader via the boot table before loading the application code. However, polling the LOCK bit in step 6 cannot be performed in the boot table. Therefore, a certain delay (e.g., 1 microsecond) can be used, as long as the PLL can successfully lock onto the phase and output a stable frequency. See the boot table structure section for the corresponding command file code.

2.3 Extended Memory Interface (EMIF)

The EMIF interface supports 8-bit, 16-bit, and 32-bit access to external data by the CPU/DMA. Supported peripherals include asynchronous memory (SRAM, ROM, FLASH memory), synchronous dynamic memory (SDRAM), and synchronous burstable SRAM (SBSRAM). Memory byte order is only supported in big-endian mode.

In the image processing card, the CE1 memory space of the EMIF is connected to the DSP's program FLASH, and the CE2 space is connected to the SRAM through the CPLD memory switching module. The memory access reference clock is selected as ECLKOUT1, with a clock frequency of 100MHz.

EMIF provides programmable control over the timing of asynchronous memory, with these timing parameters implemented through the CExCTL registers of each memory space. Key parameters include:

1) Setup Time: This refers to the time from the start of a memory access cycle to the activation of the read or write strobe signal. The minimum value is 1. For the first access in a series of consecutive accesses, whether it is a single access or a burst access, the minimum value of SETUP is 2.

2) Strobe Time (STOBE): The time it takes for the read or write strobe signal to go from being active to being inactive, with a minimum value of 1.

3) Hold time: refers to the time from when the read or write strobe signal expires to the end of the access cycle, which is reserved for the address bus to change time. The minimum value can be 0.

These timing parameters are based on SYSCLK3 (ECLKOUT1). EMIF provides independent SETUP, STOBE, HOLD times for each CE memory space read and write access.

The EMIF always performs 32-bit reads and writes each time. For 16-bit wide memory, it performs two consecutive 16-bit reads and writes. The timing diagram of the EMIF of TMS320VC5502 for reading and writing 16-bit wide memory is shown in Figure 1.

Figure 1 (a) Timing of 16-bit width asynchronous memory read from EMIF interface

Figure 1 (b) EMIF interface 16-bit width asynchronous memory write timings

EMIF automatically adds a CE read hold time after a single read or burst read operation on the same CE memory space. This time cannot be programmed and its size, along with the last read hold time, is 12 SYSCLK3 clock cycles (as shown in Figure 1a). During memory write operations, a CE write hold time is automatically added after a single write or burst write operation on the same CE memory space. This time also cannot be programmed and its size, along with the sum of all SETUP, STOBE, and HOLD times, is at least 11 (as shown in Figure 1b). When the sum of all SETUP, STOBE, and HOLD times is greater than 11, the CE write strobe time is 0.

In this image processing card, the DSP program memory FLASH uses SST Semiconductor's SST39VF400A. The SST39VF400A is a NORFLASH, allowing program code to run directly within it. It has a 256Kb×16 layout, totaling 4Mbit. The entire memory is divided into 256 regions, with a read access cycle of 70ns. According to the EMIF boot method requirements, the SST39VF400A is configured in the CE1 memory space, with a 16-bit word address space of 200000H-23FFFFH. After reset, the DSP's boot loading code loads the user application code from the external FLASH into the internal RAM according to the boot table, and then jumps to the program entry point for execution.

To ensure these parameters function correctly when loading external program code, they must be modified via the bootloader in the boot table. Sufficient delay must be maintained to stabilize the output clock. The DSP's external SRAM, CY7C1061AV33, is configured in the CE2 memory space as image memory, with a 16-bit word address space of 400000H-4FFFFFH. For reading operations from the CY7C1061AV33, the /ARE pin of the VC5502EMIF is not used; instead, /AOE is directly connected to the /OE pin of the CY7C1061AV33. In this case, the address signal, chip select /CE1, and output enable /OE are simultaneously provided. The CY7C1061AV33 is in continuous read mode, and data output is controlled only by the address bus. When the address bus changes, the data for the corresponding cell is output. The read timing of the CY7C1061AV33 is shown in Figure 2.

Figure 2 CY7C1061AV33 memory read timings

The timing requirements for read operations can be satisfied by setting SETUP=1, STOBE=1, and HOLD=0.

For write operations on the CY7C1061AV33, this application uses /WE and /OE control modes, with /OE held high. As shown in the CY7C1061AV33 write timing diagram, the CE2CTL write operation with SETUP=1, STOBE=1, and HOLD=0 meets the SRAM write timing requirements. (See Figure 3).

Configure CE2CTL as follows (MTYPE=0001b, table shows 16-bit width asynchronous SRAM).

Figure 3 CE2CTL Register Settings

Since there is no access to the CE2 memory space SRAM during system startup and loading, CE2CTL can be recorded in the startup table using a hexadecimal conversion command file and a hexadecimal conversion tool, and then modified by the Bootloader.

2.4 Booting into Boot Mode

The VC5502's on-chip ROM has several pre-programmed partitions containing the following code or content:

Startup loader; startup mode jump table; Sin function value lookup table; interrupt vector table.

The bootloader jumps to the corresponding boot mode via the boot mode jump table to execute code. The selection of the boot mode is determined by the state of BOOTM[2:0] during system reset. The relationship between BOOT[2:0] and boot modes is shown in Table 2 below:

Table 2 Relationship between BOOT[2:0] and Startup Mode

In this project, BOOTM=[2:0] is selected, and the EMIF port 16-bit extended Flash boot mode is adopted. Upon reset, the MPNMC bit of the ST3 status register is cleared, indicating that the on-chip ROM is mapped to FF_8000-FF_FFFFh. The CE1 memory space is configured as 16-bit wide asynchronous memory, and the boot loader code loads the user program code from it into the internal RAM and jumps to the entry point for execution.

During startup, the TMS320VC5502 samples the states of GPIO4, GPIO6, and GPIO7 pins. The states of these pins determine the selection of the EMIF clock source and the multiplexed interface. The impact of the GPIO4, GPIO6, and GPIO7 pin states on system configuration during reset is shown in Table 3.

Table 3 Relationship between GPIO4, GPIO6, GPIO7 and system configuration

2.5 Target Program Location and Startup Table Generation

The memory space mapping of the DSP target program is generated by the user through the linking command file. It can be used by a hexadecimal conversion tool to generate a download file or edit the memory space mapping based on the conversion command file.

2.5.1 Target Program Location

There are three ways to locate a program: compile-time location, link-time location, and load-time location. DSP systems use link-time location. The compiler divides the entire program into several sections and addresses each section starting from address 0. The linker merges sections with the same name and performs the actual location according to the section commands in the linker command file (.cmd).

The linker command file instructs the linker on how to generate memory image files (.map) and executable output files (.out) (COFF object modules). The linker command file primarily instructs the linker to perform two functions: first, how to merge input sections into output sections; and second, how to locate the output sections in the actual memory space. The linker command file achieves these functions through the MEMORY and SECTIONS commands. The MEMORY command describes the actual hardware resources of the system; the SECTIONS command describes how sections are located on appropriate hardware resources, and in this command, the load address and runtime address of the section can be defined.

In the CCS Compilation tab, select Compiler type 55x; in the Link tab, select Runtime Initialization as the Automatic Initialization method. This will cause the linker to generate code that initializes the .bss data section with padding data at runtime; in the Link tab, enter a filename in the map filename field to generate a link mapping file, which is used to check the compilation, linking, and addressing results.

After compiling and linking the project, a COFF format executable file is generated. This file is an executable image, not a dump of code that runs directly in memory. It is necessary to use hex55.exe to extract the section data information, and then, in conjunction with the hex55 command script file, reorganize the data in the form of a startup table in the hex file. Then, it is downloaded to FLASH. After the TMS320VC5502 starts, the on-chip bootloader loads it into RAM for execution.

2.5.2 Start table generation

The boot loader loads program code from Flash memory using a boot table, which enhances the independence of the boot code loading from different loading modes. It contains information such as program sections, data sections, and register settings from the COFF file format. The boot table is generated by a hexadecimal conversion tool based on the conversion command file and the linker output file. Its structure is shown in Figure 4.

The entry address of a 32-bit program is the jump address of the program execution flow after the program is loaded into internal RAM by the bootloader.

The number of 32-bit registers to be configured refers to the number of I/O memory-mapped registers and delays that need to be configured before the application is loaded during startup.

The 16-bit register address is the address of the register to be configured, followed by the 16-bit configuration value; if a delay is required for register modification, a delay flag of 0xFFFF can be used, followed by the delay clock count.

The 32-bit byte count indicates the length of sections such as program sections and data sections (in bytes).

The 32-bit starting address indicates the starting address of the corresponding section, followed immediately by the content of that section. The section is preceded or followed by a 0-byte 32-bit boundary for faster data loading. The sections are arranged sequentially.

Figure 4 Startup table structure

The number of 32-bit all-zero bytes indicates that the last section has been reached and there are no more sections to load.

The bootloader modifies registers registered in the boot table before loading external programs and data sections. This feature provides the opportunity to modify the system clock configuration to speed up code loading and to correctly configure EMIF interface memory space parameters before executing user code.

In the script file, register modifications are implemented using the `reg_config` option, with the format:

-reg_configREG_ADDRREG_VALUE;

Delay is achieved using the `delay` option, formatted as follows:

-delayDELAY_COUNT.

The HEX55.exe hexadecimal converter can read the conversion command file and the compiled output file to construct the correct boot table. On this image processing card, the main registers that need to be modified during boot are the Phase-Locked Loop (PLL) register, the peripheral system clock divider register, and the EMIF interface CExCTL register. The conversion command file code is as follows:

−boot ;option to create a boot table

−v5510:2 ;use C55x boot table format for TMS320VC5502

−parallel16 ;boot mode is 16-bit external async mem

to shut down ECLKOUTx

-reg_config 0x0800 0x271C

-reg_config 0x0801 0x0008

-delay 0x80

;to config PLL registers

-reg_config 0x1C80 0x0048 ;PLLCSR

-delay 0x100

-reg_config 0x1C8A 0x0000 ;PLLDIV0

-delay 0x80

-reg_config 0x1C8A 0x1003

-delay 0x100

-reg_config 0x1C88 0x0004 ;PLLM

-delay 0x80

-reg_config 0x1C80 0x0040 ;PLLCSR.PLLRST=0

-delay 0x100

-reg_config 0x1C80 0x0041 ;PLLCSR.PLLEN=1

-delay 0x80

;to configure PLLDIVx registers

-reg_config 0x1C8C 0x1001 ;PLLDIV1

-delay 0x80

-reg_config 0x1C90 0x1001 ;PLLDIV3

-delay 0x80

;to config EMIF CExCTL registers

-reg_config 0x0802 0xC211

-delay 0x80

-reg_config 0x0803 0xFFF3

-delay 0x80

-reg_config 0x0808 0xC110

-delay 0x80

-reg_config 0x0809 0x1081

-delay 0x80

.............

−x ;desired output format is Tektronix format

−o bottlecheck.hex ;specify the output filename

bottlecheck.out ;specify the input file

Run hex55.exe to generate a .hex hexadecimal download file, and use the FlashBurn program to download the target code into the extension's memory.

3. Peripheral module settings

3.1 I2C Module Settings

The I2C bus is a two-wire serial bus initiated by Philips. The I2C module on the TMS320VC5502 is fully compatible with the Philips I2C bus specification (version 2.1) and can be used to initialize the internal registers of the THS8083A. Connecting the I2C bus is very simple; just connect the SCL and SDA pins of the VC5502 and THS8083A respectively. Since the I2C bus is an open-drain output, pull-up resistors are required on the SCL and SDA pins. In this application, the VC5502 operates in master transmit mode, while the THS8083A can only operate in slave transmit mode, using a transmission speed of 400kbps.

The input clock of the I2C module is SYSCLK2, the module clock is 10MHz, and the output main clock SCL is 400KHz. The relevant register settings are as follows:

*I2CPSC = 0x0004;

*I2CCLKL = 0x0007;

*I2CCLKH = 0x0008;

The TMS320VC5502 generates the start and stop bits for data transmission, set by the I2C command register I2CMDR. The local address register I2COAR of the TMS320VC5502's I2C module is set to 0x0001, and the address of the THS8083A is set to 0x0020 in the slave address register I2CSAR of the TMS320VC5502's I2C module. The I2C module indicates to the C55x core that data transmission is complete via an interrupt, setting the interrupt enable register I2CIER to 0x0010. The THS8083A has 35 registers that need initialization, and the I2C module needs to send 70 bytes, set in I2CCNT. The corresponding setting code is as follows:

*I2CMDR = 0x2E00

*I2CMDR = 0x2E20; I2CMDR.IRS=1

*I2COAR = 0x0001

*I2CSAR = 0x0020

*I2CIER = 0x0010

*I2CCNT = 0x0046

By using the addresses and initialization values ​​of the internal registers of the THS8083A as a global array of type constshort, and directly initializing the array cells with the addresses and data of the registers, each address or data occupies the high eight bits of the storage cell, while the low eight bits are filled with 0.

In the I2C interrupt handler of the TMS320VC5502, the interrupt cause I2CISRC is checked, the end-of-transmission interrupt flag in the I2CSTR register is reset, the THS8083A register table pointer is checked and updated, data is filled into the transmit register I2CDXR and shifted out via I2CXSR until the end of the register table is reached, and then the I2C module interrupt is masked. Only the lower eight bits of the I2CDXR register are valid; the higher eight bits are reserved. Data written to this register will be discarded. The 16-bit value from the global array is written to this register, and the data will then be correctly transmitted via the I2C bus. The interrupt handler snippet is as follows:

void c_int02(void)

{

......

if (I2Ctblptr == I2Ctblend)

{

*I2CIER = 0x0010 ;disenable the interrupt

}

if((*I2CISRC) & 0x0005)

{

*I2CDXR = *I2Ctblptr++;

*I2CSTR &= XRDYMASK;

}

......

}

3.2 Configuration of UART module and GPIO

After processing each image, the VC5502 outputs the image processing results via both serial communication and general-purpose input/output ports. The general-purpose output ports only indicate whether the corresponding detected object is qualified in terms of voltage levels, while serial communication can output more information about unqualified areas.

When the UART port of the TMS320VC5502 is enabled, SP1 and SP3 are used as the transmit and receive lines for serial communication, respectively. Here, a MAX232 is selected and connected to the UART to form an RS232 serial communication mode to output image processing results. The DSPUART's data receive terminal RXD is connected to the MAX232's receive output terminal R1OUT, and the UART's data transmit terminal TXD is connected to the MAX232's transmit input terminal.

The serial port transmission rate is set to 19200bps, with 1 start bit, 1 stop bit, 8 data bits, and no parity. The VC5502's UART is configured to operate in polling FIFO mode, transmitting images via serial port when the accumulated image processing results reach the set number. Relevant register initializations are as follows:

*URDLL = 0x00A3;

*URFCR = 0x00B9;

//wait for some time

*URFCR = 0x00BC;

*URLCR = 0x0003;

4 JTAG debugging interface

The TMS320VC5502 provides a JTAG interface for in-system debugging of the DSP. JTAG is an IEEE 1149.1 international standard and is widely used in in-system debugging of embedded systems.

The JTAG standard includes boundary scan and test access. The basic idea of ​​boundary scan is to add a shift register unit called a boundary scan register near the chip's input/output pins. When the chip is in debug mode, the boundary scan register isolates the chip from external inputs and outputs. These boundary scan registers allow for observation and control of the chip's input/output signals. Under normal operating conditions, these boundary scan registers are transparent to the chip. Furthermore, the boundary scan register units on the chip's input/output pins can be interconnected to form a boundary scan chain. Generally, chips provide several independent boundary scan chains to implement complete test functions. Boundary scan chains can serially input and output data, and with appropriate clock and control signals, the chip being debugged can be easily observed and controlled. Boundary scan chains belong to two types of registers in the JTAG standard: data registers and instruction registers, the latter used to control the data registers. The test access port (TAP) is a general-purpose port that provides access to all data and instruction registers provided by the chip. Control of the entire TAP is achieved through the TAP controller. TAP includes a total of five signal interfaces: TMS, TCK, TDI, TDO and TRST, which are also known as the JTAG interface [31-34].

Design a 14-port JTAG interface on the image processing card circuit board.

The following issues need to be noted:

1) The Emu0 and Emu1 pins of the VC5502 need to be pulled up;

2) To ensure a good TCK signal, a noise reduction circuit is added to the TCK signal;

3) In the 3.3V DSP, the PD pin is powered by 3.3V, but the emulator requires a 5V power supply, so the emulator needs a separate power supply.

5. Extended Flash Programming

In this application, the SST39VF400A is programmed using TI's FlashBurn software and the FBTC target component. FlashBurn communicates with the target DSP via its internal protocol, downloading the hex file obtained using a hexadecimal conversion tool to the on-chip RAM, and then the target code is programmed into the FLASH memory using the FBTC program core.

The SST39VF400A features internal programming logic circuitry, enabling convenient sector erasure, block erasure, slice erasure, and word/byte programming operations. It offers two programming cycle control modes: /WE and /CE. In /WE mode, the address and data are latched on the falling and rising edges of /WE, respectively, before the internal programming program is initiated, programming the data into the corresponding address units. The write timing diagram of the SST39VF400A is shown in Figure 5.

After processing each image, the VC5502 outputs the image processing results via both serial communication and general-purpose input/output ports. The general-purpose output ports only indicate whether the corresponding detected object is qualified in terms of voltage levels, while serial communication can output more information about unqualified areas.

When the UART port of the TMS320VC5502 is enabled, SP1 and SP3 are used as the transmit and receive lines for serial communication, respectively. Here, a MAX232 is selected and connected to the UART to form an RS232 serial communication mode to output image processing results. The DSPUART's data receive terminal RXD is connected to the MAX232's receive output terminal R1OUT, and the UART's data transmit terminal TXD is connected to the MAX232's transmit input terminal.

The serial port transmission rate is set to 19200bps, with 1 start bit, 1 stop bit, 8 data bits, and no parity. The VC5502's UART is configured to operate in polling FIFO mode, transmitting images via serial port when the accumulated image processing results reach the set number. Relevant register initializations are as follows:

Figure 5 SST39VF400A memory programming timings

Using the timing diagram Figure 1b for asynchronous memory writing in VC5502, the value of the CE1CTL register can be set when writing to FLASH. Before programming the SST39VF400A, sector erasure, block erasure, or chip erasure operations must be performed first. Because the SST39VF400A has hardware and software data protection mechanisms, to perform erasure and programming operations, the corresponding command sequence must first be used, and then the corresponding unit must be operated on. The erase and write command sequences are shown in Table 4:

During the erase and programmable processes, the SST39VF400A does not return the contents of a memory cell when reading from it. Instead, it returns the contents of an internal status register. The data query bit DQ7 and the data flip bit DQ6 of this register can be used to determine whether the erase or programmable operation has ended.

During programming, DQ7 returns the two's complement of the 7th bit of the read memory location; after programming, it returns the original code of the corresponding bit. During erasure, it always returns 0; after erasure, it returns the value of the corresponding bit. During programming and erasure, DQ6 returns an alternating sequence of 1s and 0s; after programming and erasure, it returns the corresponding bit of the read memory location. This application uses DQ6 to detect whether programming and erasure operations are complete. The code snippet is as follows.

void Check_Toggle_Ready (short *Dst)

{

......

PreData = *Dst;

PreData = PreData & 0x4040;

while ((TimeOut< 0x07FFFFFF) && (Loop))

{

CurrData = *Dst;

CurrData = CurrData & 0x4040;

if (PreData == CurrData)

Loop = FALSE; /* ready to exit the while loop */

PreData = CurrData;

TimeOut++

}

}

The programming and erasing algorithms of the SST39VF400A are implemented in the source file of the Flash Target Component (FBTC), which contains two main functions: BurnFlash() and EraseFlash(). The BurnFlash function reads the hex file to be programmed, and then sends the programming address and data to the FBTC module until the required number of bytes for programming is reached; the EraseFlash function sends commands to the SST39VF400A to execute sector, block, or slice erase commands.

After resetting the VC5502, boot in HPI mode and initialize the DSP using GEL in CCSTUDIO. The GEL file mainly completes functions such as DSP memory space configuration, input/output space configuration, and register initialization. Then start the FlashBurn program. In the download box, enter the generated hexadecimal file in the file to be burned field, enter 0x0 in the logical address field, and select the write verification checkbox. Select 55x in the target system processor type, select FBTC55.out in the FBTC program file, enter 0x400000 (in bytes) in the Flash memory physical address field, and enter 0x80000 (512K) in the number of bytes. After configuration, FlashBurn will store the configuration in a file with the extension .cdd.

The FlashBurn program communicates with the FBTC program downloaded to the VC5502's internal RAM. After verifying the DSP model, FLASH writing start address, and FLASH byte count, the hexadecimal file can be sent to the VC5502 via the JTAG port, and FBTC will be responsible for writing the data into the Flash.

6. Conclusion

The development of microelectronics and image processing technologies has spurred the advancement of machine vision-based online inspection technologies. The introduction of high-performance DSPs has made real-time processing of large-capacity image data a reality, further accelerating the development of machine vision inspection technology. The application of DSP-based image data processing methods has improved the efficiency and accuracy of empty bottle inspection, offering valuable insights for the field of online inspection.