introduction
Currently, with the continuous increase in the range, speed, flight altitude, and maneuverability of missile weapons, electric servo systems are developing towards higher output torque, faster response speed, higher power, smaller size, higher integration, and full digitalization. Brushless DC motors not only maintain the excellent dynamic and static speed regulation characteristics of traditional DC motors, but also have a simple structure and reliable operation, and have been widely used in defense, aerospace, and other fields.
The MIL-STD-1553B bus, as a data bus with high data transmission performance, management efficiency, and reliable transmission, has matured and is widely used in complex control systems such as aerospace and weaponry.
This paper takes a high-power brushless DC electric servo motor [3] as the object and designs a set of digital high-precision and high-reliability controller based on DSP+FPGA, and realizes the 1553BRT terminal access function.
1. Overall Design Scheme of Servo System
The servo system employs a three-loop control strategy encompassing position, speed, and current. The overall hardware design is shown in the figure. The specific operation is as follows: The DSP reliably communicates with the main control computer via a 1553B communication module. It acquires rotor position, speed, and actual servo deflection angle signals through rotor position and servo deflection angle detection circuits. Combined with the phase current sampled by the built-in ADC module, the signals are processed by the three-loop control algorithm, outputting a modulated PWM signal that drives the brushless DC motor. The flexible configurability of the FPGA is utilized to design the hardware logic circuits for timing control of each main functional chip, including the 1553B communication module, rotor position and speed detection circuit, and servo deflection angle measurement circuit. This significantly reduces DSP software overhead and improves CPU efficiency.
Figure 1 Overall hardware structure diagram of the servo system
2 Hardware Circuit Design
2.1 DSP Main Control Unit
The main controller uses the 32-bit fixed-point digital signal processor TMS320F2812 from TI (Texas Instruments) [4]. This chip uses a Harvard bus architecture, separating the data bus and the program bus, and can execute 150 million instructions per second (150 MIPS). It has a single-cycle 32x32-bit multiplication and accumulation (MAC) operation function. For motor control applications, it integrates two powerful event managers (EVA, EVB) and a 16-channel high-speed ADC module.
Logic control unit
The FPGA logic chip selected is Altera's Cyclone II series EP2C8T144C8. The Cyclone II is an FPGA chip based on the Stratix II 90nm process, featuring 8256 logic elements (LEs), 36 built-in M4K RAM blocks, 2 phase-locked loops (PLLs), and 18 multiplier modules, providing users with 85 usable I/O pins. This chip is primarily used in conjunction with a DSP to implement logic control functions.
Bus communication module design
The BU-61580[5] from DDC was selected as the 1553B bus communication protocol chip. The chip integrates digital protocol control circuit, dual-channel bus transceiver and other modules. The FPGA only needs to operate the 17 general registers and 4KX16bit RAM of the protocol chip. The protocol chip can automatically complete the entire communication process. The circuit connection between BU-61580 and FPGA is shown in the figure. The 74LVC4245 chip is used for logic level matching. TRANSPARENT/BUFFERED is pulled low to set BU-61580 to 16-bit buffer working mode. The FPGA directly uses the chip's internal 4KX16bit shared RAM.
Figure 2 shows the circuit connection diagram between BU-61580 and FPGA.
Power drive module design
The functional drive module uses Fuji's 7MBP75RJ120. This IPM module can withstand voltages up to 1200V and currents up to 75A, and internally features undervoltage, overheat, overcurrent, and short-circuit protection. The specific circuit connection is shown in the figure. The DSP outputs six PWM signals, which drive the IGBTs inside the IPM via a high-speed, high common-mode ratio optocoupler chip HCPL-4504, thereby controlling the three-phase voltages U, V, and W of the brushless motor. Fault signals are transmitted to the DSP interrupt port via an optocoupler chip TLP521-1. The power supply uses four independent WRB0515 DC power supply modules.
Figure 3. Circuit connection diagram of IPM power drive module
Rotor position detection circuit
The rotor position and speed detection adopts a combination scheme of rotary transformer and decoding chip. The Tamagawa TS2620N21E11 rotary transformer [6] is used, with input voltage AC7Vrms10KHz, transformation ratio 0.5±5%, and maximum error accuracy ±10′. The decoding chip is the 12-bit resolution rotary transformer-angle-speed digital converter FB9412PB of Feiboer. This converter has a 10kHz excitation power output, directly converts the sine and cosine analog signals output by the rotary transformer into angle and speed digital signals, and outputs them in parallel port mode. The data resolution is 5.3′, the accuracy reaches ±7.8′, and the maximum tracking speed is 1000rps. The terminal connection of FB9412PB and rotary transformer is shown in Table 1.
Table 1. Terminal Connection Relationship between FB9412PB and Rotary Transformer
FB9412PB terminal | TS2620N21E11 terminal | Terminal color |
Excitation power supply output RH | Excitation power input | Red and white |
Excitation power supply output RL | Excitation power input | Yellow and white |
Sin signal input terminal SIN | Sine wave output terminal | yellow |
Sine wave input terminal SINL | Sine wave output terminal | blue |
Cosine signal input terminal SIN | Cosine signal output terminal | red |
cosine signal input terminal SINL | Cosine signal output terminal | black |
Current detection circuit
The phase current is detected using an LEM HMS20-P Hall effect current sensor with a measurement range of ±60A, an output voltage range of 2.5V ± (0.625 × 20)V, and a response time of less than 5µs. The circuit principle is shown in the figure. The LEM output Vout and reference output Vref are scaled down by an integrated operational amplifier OP27 at a 3:4 ratio and then connected to the DSP's ADCINA0 and ADCINB0 terminals. Subtracting the two values reduces the influence of temperature and measurement errors.
Figure 4 LEM current detection circuit connection diagram
Deflection detection circuit
The electric servo motor converts the rotational motion of the brushless DC motor into linear motion through a transmission gearbox and ball cylinder, driving the nozzle to oscillate. The nozzle oscillation angle can be determined by measuring the displacement of the ball cylinder. An EQN425 multi-turn absolute encoder manufactured by Heidenhain GmbH (Germany) is selected, with a rotation speed of 4096 revolutions, 8192 positions per revolution (13 bits), a calculation time of 0.5µs, and an accuracy of [insert accuracy here]. The encoding type is Gray code, and the output signal is a synchronous serial signal (SSI). The SSI208P SSI interface to parallel port module is selected. This module automatically converts the synchronous serial interface signal (SSI) into 8-bit parallel port data, with a data update rate greater than 100kHz.
Limit protection circuit
The maximum limit protection circuit is implemented by limit switches installed at the maximum forward and reverse strokes of the motor's lead cylinder, using Haili Z15G1 micro switches. When the lead cylinder reaches its maximum stroke, the corresponding switch is activated, and a fault signal is transmitted to the DSP chip's interrupt port, directly shutting down the six PWM channels.
3 Software Design
The control system software design mainly includes two parts: DSP main control program design and FPGA logic control program design. The DSP program is written in C language and compiled using CCS 3.3. The FPGA program is written in Verilog language and compiled using Quartus II.
3.1 DSP Main Program Design
The DSP primarily implements the main program of the control system and the three-loop digital PID control algorithm for current, position, and speed. The FPGA transmits the received control surface deflection signal and the acquired rotor position, speed, and actual control surface deflection angle to the DSP. The DSP, combined with its own ADC sampling current signal, processes the signal through the algorithm and outputs a modulated PWM. The program flow is shown in Figure 5.
Figure 5 DSP main program flowchart
3.2 FPGA Logic Programming
The FPGA program adopts a modular design concept [7] and implements the BU-61580 RAM read/write control timing, FB9412PB control timing, SSI208P control timing and DSP interface control logic. The timing control of each module is shown in Figure 6-11.
Figure 6 CPU RAM read timing (16-bit buffer, non-zero wait mode)
Figure 7 FPGA RAM read timing simulation
Figure 8 FB9412PB Control Timing
Figure 9 Timing simulation of FB9412PB
Figure 10 SSI208P Control Timing
Figure 11 SSI208P timing simulation
4. Conclusion
This paper designs and implements a high-power brushless DC electric servo controller based on 1553B bus communication. It utilizes the high-speed computing performance of a DSP to implement a three-loop control algorithm for current, speed, and position. The timing logic control circuit is designed by fully leveraging the flexible configurability of an FPGA, and the 1553BRT terminal controller is implemented using the BU-61580 protocol chip. Practical applications demonstrate that this controller exhibits high control accuracy and fast adjustment speed, possessing significant engineering application value.
