Abstract : The BiSS communication protocol is a full-duplex synchronous serial bus communication protocol specifically designed to meet the needs of real-time, bidirectional, and high-speed sensor communication. It is hardware-compatible with the industry-standard SSI (Synchronous Serial Interface) bus protocol. Its typical application is in motion control, enabling communication between servo drives and encoders.
Current Status and Development Trends of Encoder Buses
With the development of fieldbus technology and the increasing prevalence of System-on-Chip (SoC), fully digital control systems have become a development direction and research hotspot in this field. Encoders are also evolving towards digitalization, leading to technological advancements in absolute encoders and related communication buses. Since encoders are most widely used in motion control, encoder buses must meet the motion controller's requirements for accuracy, resolution, and response speed, and should include the following characteristics:
1. High-speed communication
2. Fixed time delay
3. Data Diagnostics
4. Two-way communication
5. Low cost
High-speed communication helps improve response speed; the accuracy and resolution of the encoder determine the accuracy of the control system, and latency is a crucial factor affecting encoder accuracy. Ideally, the time between the motion controller issuing a "read command" and the encoder starting sampling should be fixed. The smaller this latency, the more accurate the physical meaning of the encoder's encoded value, which is beneficial for servo controller algorithm adjustment.
Consider a scenario where encoder communication is implemented using a CAN bus. First, the servo controller sends a CAN communication frame; then, the encoder extracts the "read command" from the CAN communication frame; finally, the encoder samples the data and sends it back. What is the sampling lag in this process, and is the duration fixed? In contrast, BiSS samples data on the first rising edge of MA (MA is the clock signal from the host), theoretically with no delay.
It can be said that general-purpose fieldbuses are currently not suitable for high-speed encoder communication. Sensor buses specifically designed for high-speed data communication are mostly developed by encoder manufacturers and are highly closed systems. Representative bus communication protocols include EnDat2.2 , Hiperface, SSI, and NRZ. BiSS is an internationally recognized and open protocol. The current version of the BiSS communication protocol is BISS-C. Using BISS requires no licensing fees, and BiSS association members can apply for free IP core source code and related technical support. Maintaining BiSS association membership is free, and membership application is also free.
Key technical features of the BiSS communication protocol
1. Two-wire serial synchronous data bus with RS422 interface and baud rate of 10 Mbit/s; or LVDS interface with baud rate >10 Mbit/s, reflecting the high response speed of BiSS;
2. High communication efficiency, transmitting over 64 bits per 10µs with an effective load factor greater than 80%. This reflects BiSS's ability to handle high-resolution encoder data;
3. Time-division multiplexing of the line includes a data communication channel that transmits one frame per communication cycle and a register communication channel that transmits one frame bit per communication cycle. Register communication and data communication are completely independent and do not interfere with each other. For applications that do not require register communication, the BiSS-CUnidirectional version can be used. This version of the protocol does not include register communication.
This reflects the better stability and convenience of the control system using BiSS.
4. Multiple security mechanisms ensure data reliability. BiSS's delay compensation technology compensates for signal delays caused by transmission lines, and two sets of CRC generator polynomials are used to verify sensor data and register data respectively. The BiSS protocol frame also includes an alarm bit and an error bit, and the CRC generator polynomial can be customized. A 6-bit CRC is sufficient for most applications, while for high-security applications (such as those requiring compliance with European safety standards), BiSS can use a 16-bit CRC.
This reflects that BiSS transmission is more reliable, and control systems using BiSS are more reliable.
5. Data synchronization: BiSS uses a clock signal to synchronize sensor data. The sensor updates its data when the first clock pulse arrives. The transmission delay of each frame of data arriving at subsequent electronic devices is the same, which facilitates delay compensation by subsequent electronic devices. It is particularly suitable for applications with strict requirements on time and position relationships, such as motor control.
This reflects that BiSS has little impact on encoder accuracy, which helps improve the high-speed characteristics of the control system.
6. Networking capability: BiSS can be used to form a single-bus sensor ring network, collecting all sensor data in one communication cycle, and the signal acquisition is synchronous.
This reflects the scalability and forward-thinking nature of BiSS.
7. Plug and play: BiSS supports reading encoder parameters from registers to configure data communication. Any encoder and control system that supports BiSS standard EDS and Profile can communicate directly without modifying any program.
This reflects BiSS's high degree of openness and compatibility.
Basic content of BiSS communication protocol
1. Network topology
Figure 1 illustrates the basic networking method of BiSS, called point-to-point mode. The downstream electronic device (PLC in the figure) provides a clock signal to the sensor via a differential signal, and the sensor synchronously transmits sensing data to the downstream electronic device via a differential signal. In the BiSS protocol, the downstream electronic device is called the Master, and the sensor is called the Slave. In point-to-point mode, the Master can receive data from the Slave and simultaneously engage in bidirectional data communication with the Slave.
Figure 1 Point-to-point networking
Figure 2 illustrates the multi-slave networking configuration of BiSS. The Master can complete communication with multiple Slaves within a single cycle. All devices are connected in a daisy-chain configuration. Each Slave has two ports, one for receiving signals from the front-end and the other for sending signals to the back-end. This is a pipeline-like operation; each Slave receives data from the previous Slave and places it at the end of its own transmit queue, while simultaneously prioritizing the transmission of its own data. The entire communication is synchronized by a clock signal from the Master. The Master serially shifts Actuator data into each Slave via the MO signal and sequentially receives data from each Slave via the SL signal.
Figure 2 Multi-slave Networking
2. BiSS frame structure and data communication
Figure 3 illustrates a BiSS communication frame in a point-to-point network. MA is sent by the Master to drive communication, and SL is the data signal sent by the Slave. The completion of one BiSS communication frame indicates that the Master has received one frame of data.
Figure 3. BiSS frame structure of point-to-point networking.
Figure 4 depicts the BiSS communication frame of a Multi-slave Networking network. Each Slave not only needs to send its own data, but also needs to receive and forward the data sent by the previous Slave.
Figure 4. BiSS frame structure of Multi-slave Networking
The BiSS communication process can be described as the switching of the following states: IDLE, StartFrame, Transmission, and Timeout.
IDLE indicates an idle state; BiSS communication is idle, MA and SL are kept high.
StartFrame, the start of frame communication: MA sends a clock signal. On the first rising edge of MA, the Slave latches the sensor state. On the second rising edge of MA, the encoder pulls SL low to acknowledge the Master's communication request.
Ideally, the time delay between the low-level pull of SL and the second rising edge of MA is minimal. However, in practical systems, due to the combined effects of long line delays, signal shaping, filtering, and the transmission through multiple gate circuits, SL experiences a phase shift relative to MA, causing SL to lag behind the second rising edge of MA by a certain amount of time. This time is called the line-delay. If the SL signal sampling circuit cannot correct this delay, the communication distance and rate of the bus must be reduced to ensure reliable sampling of the SL signal. BiSS specifies that the line-delay must be checked and corrected at the beginning of each communication frame, thereby ensuring that the BiSS communication baud rate can reach 10 Mbit/s.
During the line-delay period, MA continuously outputs pulses.
Transmission: After the SL signal is pulled low from its normal high position, it remains low for a period of time. This period is called ACK, indicating that the Slave has responded to the MA signal and is preparing data. ACK typically lasts between 0.1µs and 8µs, depending on whether the Slave is ready for data transmission. For a specific Slave, the ACK length is essentially fixed. During the ACK period, MA continuously outputs pulses. When SL sends a 1-bit START bit (constantly '1'), it indicates that the Slave is ready for data transmission. Data transmission begins.
The SL will sequentially send one bit of CDS signal and one single-cycle field (SCD); BiSS specifies that the single-cycle field length must be greater than 4 bits and less than 64 bits. For specific applications, the field length is specified by the slave manufacturer (e.g., the single-cycle bit field of Yuheng's multi-turn encoder includes 16 bits of multi-turn count, 17 bits of single-turn position, 2 bits of error alarm, and 6 bits of CRC check). During this period, the MA continuously outputs pulses.
Timeout: After the SCD is sent, SL remains low for 0.5~40us . This period is called the Timeout. For specific applications, the Timeout is specified by the Slave manufacturer. MA sends the CDM signal during the Timeout period, and this signal is maintained until SL is pulled high. After SL is pulled high, the communication is completely over.
2. Register communication in BiSS
CDM and CDS are signals used for register communication between the Master and Slave. After several cycles of data communication between the Master and Slave, the CDM sequence sent by the Master and the CDS sequence received by the Master constitute a BiSS register communication frame, as shown in Figure 5.
Figure 5 shows a register communication sequence consisting of multiple BiSS frames.
Figures 6 and 7 illustrate the BiSS register communication read/write timing. The timing diagrams demonstrate that BiSS can exchange data bidirectionally with the encoder. BiSS register communication includes CRC checksum and read-back checksum (for write timing).
BiSS's register communication consumes very little bandwidth, giving it an advantage over EnData2.2 and NRZ. This is because servo controllers read encoder parameters frequently during initialization, while during normal operation, users typically only focus on error alarm information. BiSS places error alarm information in high-real-time data communication, using CDS and CDM to handle time-consuming register communication. This method of designing different communication rates based on data real-time requirements significantly saves communication bandwidth and effectively reduces communication latency. Therefore, using a BiSS encoder can result in better control performance.
Figure 6. BiSS Register Communication Write Timing
Figure 7. BiSS Register Communication Read Timing
Implementation method of BiSS communication protocol
1. Hardware Decoding
For users employing hardware decoding, they can choose the decoding chip provided by IC-HAUS or use the IP soft core provided by IC-HAUS for decoding, depending on their needs. Alternatively, an MCU with an IP hard core can be selected. If the IC-HAUS IP soft core is used to implement both data communication and register functions, FPGA decoding is required. The FPGA resource count needs to be greater than 1300 LEs (the compilation result when the BiSS-MCU interface is set to SPI) or equivalent. If only data communication is desired, CPLD decoding can be used. The CPLD resource count needs to be greater than 96 LEs (more than 150 LEs are needed after adding a clock divider circuit and SPI interface) or equivalent. A challenge in self-design is handling line delay. For applications with very short or no external leads, the line delay variation is small. In this case, a sampling clock with a fixed delay can be designed; otherwise, line delay compensation must be performed every cycle.
2. Software decoding
Users can simulate BiSS timing via I/O, but this method is not recommended. It is recommended to use the MCU's hardware peripheral decoding, which allows for high BiSS communication speed settings. This also saves on the cost of external logic circuits, which is considerable for many applications, and offers advantages for product standardization. A powerful general-purpose serial decoding module, using different decoding programs, should support multiple serial communication protocols, full-duplex, half-duplex, etc. For example, for BiSS, SPI's SCK can be used to simulate MA, and MISO can simulate SL. This approach requires consideration of three issues:
1. FIFO depth of the MCU hardware module. Some MCUs have a fixed SPI register length for their peripherals, requiring multiple communications and interruptions to complete one frame of BiSS communication. This results in discontinuous MA waveforms, which can cause communication errors.
2. Does the MCU hardware module have line delay compensation capabilities? Peripherals with line delay compensation capabilities can cope with the impact of changes in the actual application environment, such as changes in requirements, environmental changes, circuit aging, etc. Systems with line delay compensation have much higher reliability and adaptability than systems without it.
3. CRC decoding capability: CRC verification places demands on the MCU's processing capabilities.
When using an MCU for decoding, it is essential to thoroughly examine the characteristics and processing capabilities of different MCU peripherals, as well as the strength of technical support from the chip manufacturer and whether there is a mature design, etc.
3. Hybrid Decoding
If you want to utilize hardware decoding while reducing costs, you can use a hybrid decoding approach. For example, you can use some resources of an FPGA or CPLD to handle data communication, while exporting the CDM and CDS signals for processing by the MCU. This approach is a transitional but practical solution. It's important to note that the CDM signal must be ready before communication is initiated. With the development of MCUs and FPGAs, this approach will gradually be phased out to reduce coupling between systems.
4. BiSS Communication Frame Example
Figure 8 shows an example of a BiSS communication frame to help readers intuitively understand the BiSS communication process.
Figure 8: Example of a BiSS communication frame
Comparison of BiSS communication protocol with other communication protocols
As shown in Table 1 below, the BiSS communication protocol has leading advantages in protocol availability, network architecture (connectivity, master/slave count, multi-slave synchronization), and line delay compensation, while its transmission rate and minimum cycle time are comparable to Endat2.2 . Furthermore, BiSS's data communication and register communication occupy separate communication channels and do not interfere with each other.
Table 1 Comparison of parameters for different encoder protocols
Current Status and Development of BiSS Communication Protocol
The BiSS communication protocol has been widely used in Europe and supported by major driver and encoder manufacturers in China after more than a decade of development. BiSS was launched in Europe in 2002, and the BiSS decoding chip IC-MB3 was released in 2003. A unidirectional version of BiSS was released in 2009. The BiSS bus frame format has remained stable, and numerous encoder manufacturers have launched encoder products based on BiSS. Currently, more than 278 manufacturers worldwide are members of the BiSS protocol.
Europe is a trendsetter in industrial control, with the development of protocols such as CiA402 and IEC61131-3, and open protocols are becoming increasingly popular. BiSS has taken the lead, bringing users numerous benefits such as compatibility, low cost, and stability. It is poised for even greater development in China in the future.
