Abstract : This paper introduces the host hardware structure of an ARM-based embedded temperature control system and the slave hardware structure of an AVR-based embedded temperature control system. 8MB of FLASH and 32MB of SDRAM are selected as system memory, and peripheral communication devices such as Ethernet and serial interfaces, as well as input/output interfaces, are expanded. The slave device uses an Atmega128 series microcontroller to complete temperature acquisition and data transmission to the host. The AT91RM9200 communicates with the Atmega128 via a serial port. This embedded temperature control system features strong scalability, high reliability, fast response speed, and small size.
Keywords : Hardware components, AT91RM9200, memory, interface circuit, Atmega128
Temperature measurement and control have wide applications in embedded industrial production. Currently, control schemes mainly use traditional PLCs and microcontrollers , meeting the needs of most users. PLCs are primarily designed for single projects or projects with very few repetitions , lacking flexibility , and are also bulky and relatively expensive . Microcontrollers, on the other hand, are mainly used for controlling small devices , especially professional electronic equipment , offering advantages such as low cost , low power consumption , and high efficiency . However, they also have drawbacks such as the inability to modify the program after it has been copied once , limited control over peripheral devices , and poor anti-interference capabilities. This paper presents a novel control scheme using embedded technology.
I. Hardware Components of the Host
The host hardware design of the ARM-based embedded temperature control system consists of the following main components:
1. Power supply circuit: The input is 5V, which is converted to 1.8V and 3.3V through DC-DC conversion to provide operating voltage for various components in the system.
2. Crystal oscillator circuit: The 18.432MHz active crystal oscillator is multiplied to provide a clock frequency of 180MHz for the ARM940T core/system.
3. Microprocessor: namely AT91RM9200, which is the working and control center of the system.
4. Memory: It can store the boot program, embedded operating system, user application program or other data that needs to be saved after the system loses power.
5. Network port: 10J100Mbps RJ45 interface, providing a physical channel for Ethernet access to the system.
6. Serial interface: Used for short-distance bidirectional serial communication in the AT91RM9200 system.
II. Hardware Design of the Host
1. Power supply circuit
The AT91RM9200 requires 1.8V and 3.3V power supplies. Additionally, most peripheral components require 3.3V , and a small number require 5V. Therefore, Sipex SPX1117M3-3.3 and SPX1117M3-1.8 low-dropout (LDO) regulators were used for DC-DC conversion to provide operating voltages for the various components.
2. Crystal oscillator circuit
The crystal oscillator circuit is used to provide the clock to the AT91RM9200 microprocessor, as shown in Figure 1. This system includes two crystal oscillators, passive crystal oscillators X1 ( 18.432MHz ) and X2 ( 32.768kHz ), serving as the system's main oscillator and slow clock oscillator, respectively. The 32.768kHz crystal oscillator provides the system's slow clock, while the 18MHz crystal oscillator, after frequency multiplication, provides the system's 180MHz master clock.
Figure 1 Crystal oscillator circuit
Fig1Circuitofcrystaloscillator
3. AT91RM9200 processor
It is a high-performance, low-power 16/32-bit RISC microprocessor from Atmel, based on the ARM920T core. Its maximum clock speed is 180MHz, and its bidirectional, 32-bit external data bus supports 8-bit, 16-bit, and 32-bit data widths. Its 26-bit address bus can address up to 64MB of memory. It is the system's operating and control center.
4. Memory
The memory module consists of two parts: Flash memory and SDRAM memory.
FLASH memory is used to store boot programs, embedded operating systems, user applications, and important data. Even when power is lost, the programs and data are not lost. The design uses the Intel 28F640J3A chip, which has a storage capacity of 64 Mbit (8 MB), an operating voltage of 2.7V to 3.6V , a 48-pin TSOP package, and a 16-bit data width.
SDRAM memory is the place where system code runs, storing programs and data during system operation, but these programs and data will be lost after power failure [3]. In the design, two 16-bit SDRAM chips are used to run in parallel as a 32-bit SDRAM module , as shown in Figure 2. The SDRAM circuit used is Hynix's HY57V651620BTC, which has an operating voltage of 3.3V , a single chip storage capacity of 4 groups × 16Mbit, a 54-pin TSOP package, is compatible with LVTTL level interface, and supports automatic refresh and self refresh.
Figure 2 SDRAM memory system block diagram
Fig. 2 Frame chart of SDRAM system
5. Interface circuit
(1) Network port: The DAVICOM DM9161 is used as the physical layer interface for Ethernet. Through this interface, many physical layer devices can be controlled and configured, status and error information can be obtained, and the working mode and function of the PHY device can be determined.
(2) Serial Interface: Used for short-distance bidirectional serial communication of the AT91RM9200 system. The level conversion circuit used is the SP3232E from Sipex. This system includes one UART interface, which is a two-wire debug serial port used to connect to a terminal emulator to observe the startup of the AT91RM9200 and complete communication debugging with the PC. Its schematic diagram is shown in Figure 3.
Figure 3 Serial interface circuit
Fig3 Serialinterfacecircuit
(3) Ethernet interface circuit
In this design, the DAVICOM DM9161 is used as the physical layer interface for Ethernet, handling encoding, decoding, and outputting data. The DM9161 also provides the MII (Mild Interface ) defined by the IEEE 802.3 standard to control data transmission between the physical layer and the MAC layer. The DM9161 uses a simple two-wire serial interface to control the physical layer and receive information from it via the MII. Its serial control interface includes MDC (Data Clock) and MDIO (Data Input/Output). The MII serial management includes a data interface, basic register settings, and a serial interface for register settings. Through this interface, various physical layer devices can be controlled and configured, status and error information can be obtained, and the operating mode and function of the PHY devices can be determined.
Connect the REF_CLK pin of the DM9161 to the output of a 50MHz crystal oscillator; connect the TXDI, TXD2, TXEN, RXD1, and RXD2 pins of the DM9161 to the ETXO, ETXI, ETXEN, ERXO, and ERXI pins of the AT91RM9200; connect the EXesEN, COL, and PWRDWN pins of the DM9161 to a high level through 10K resistors, and connect a 6.8K resistor between BGRESG and BGRES; connect the RXesDV, RXER, RESET, MDC, and MDIO pins of the DM9161 to the ECRS, ERXER, NRST, and EMDIO pins of the AT91RM9200, all connected to LEDs; connect the TX+, TX-, RX+, EMDC, FDX, SPEED, and LINKRX pins of the DM9161 to a network isolation transformer.
III. Slave Hardware Composition and Design
1. ATmega128 microcontroller
Atmel's AVR microcontroller is an enhanced RISC microcontroller with on-chip Flash memory. It features 128KB of in-system programmable Flash (with read-while-write capability, i.e., RWW), 4KB of EEPROM, 4KB of SRAM, 53 general-purpose I/O lines, 32 general-purpose working registers, a real-time clock (RTC), four flexible timer/counters (T/C) with compare mode and PWM functionality, two USARTs, a byte-oriented two-wire interface (TWI), an 8-channel 10-bit ADC (with selectable programmable gain), a programmable watchdog timer with an on-chip oscillator, an SPI serial port, a JTAG test interface compliant with the IEEE 1149.1 standard, and six software-selectable power-saving modes.
2. System control and reset
Upon reset, all I/O registers are initialized, and program execution begins at the reset vector. The instruction at the reset vector must be an absolute jump (JMP) instruction to cause the program to jump to the reset handler routine. If the program never enables interrupts, the interrupt vector can be overridden by regular program code.
Figure 4 shows the circuit diagram of the reset logic.
Figure 4 Reset logic circuit diagram
Fig4 Replacementlogiccircuit
3. I/O ports
When used as general-purpose digital I/O, all AVRI/O ports have true read-modify-write functionality [5]. The output buffer has symmetrical drive capability and can output or sink large currents to directly drive LEDs.
4. SPI serial peripheral interface
The Serial Peripheral Interface (SPI) allows for high-speed synchronous data transmission between the ATmega128 and peripherals. The SPI connection between the master and slave devices is shown in Figure 5.
Figure 5. SPI connection between master and slave devices
Fig5SPIconnectionofmainengineandfrommachine
5. 16-bit timer/counter
The 16-bit T/C enables precise program timing, waveform generation, and signal measurement. The normal mode, CTC mode, fast PWM mode, and phase-corrected PWM mode of T/C1 and T/C3 are the same as those of T/C0 and T/C2.
6. A/D, D/A circuit
The TLC2543 is a 12-bit analog-to-digital converter (ADC) with serial control and 11 inputs. Connect the microcontroller's PC0 port to the TLC2543's chip select (CS) pin, PC1 port to the TLC2543's data output (DATAOUT) pin, PC2 port to the TLC2543's address input (DATAINPUT) pin, and PC3 port to the TLC2543's input/output clock (I/OCLOCK) pin. Use an OP07 microcontroller to build an analog signal amplification circuit to amplify the received sensor signal. Connect the TLC2543's AIN0 pin to the amplified analog signal to complete the A/D conversion. The specific wiring between the TLC2543 and the microcontroller is shown in Figure 6.
Figure 6. Connection diagram between TLC2543 and microcontroller
Fig6connectiondiagramofTLC2543andmicrocontroller
The TLC5615 is a 10-bit serial three-wire digital-to-analog converter (DAC). This controller connects the microcontroller's PB0 port to the TLC5615's chip select pin, PB1 to the TLC5615's serial clock input (SCLK) pin, and PB2 to the TLC5615's serial data input (DIN) pin. The TLC5615's DAC analog voltage output (OUT) is connected to the inverter's frequency modulation ratio terminal to complete the D/A conversion. The specific wiring diagram between the TLC5615 and the microcontroller is shown in Figure 7.
Figure 7. Connection diagram between TLC5615 and microcontroller
Fig7connectiondiagramofTLC5615andmicrocontrolle
4. Conclusion
Temperature control is achieved using Atmel's AT91RM9200 32-bit ARM9 embedded microcontroller and Linux operating system. This system features strong scalability, high reliability, high measurement and control accuracy, real-time multi-task scheduling, fast response speed, and small size, making it a cost-effective temperature control system.
