Many users have some questions about the high-speed counting function of the Yiwei UN200 CPU. Below, I will share some of my experiences to help you better understand and apply this function. First, please note that the Yiwei UN200 CPU high-speed pulse counter accepts encoders with a 24V input level; both NPN and PNP outputs can be connected. Ordinary counters are affected by the CPU's scan speed and operate in a sequential scanning manner. In each scan cycle, the counting pulse can only be accumulated once. If the frequency of the pulse signal is higher than the CPU's scan frequency, using an ordinary counter will inevitably result in the loss of many input pulse signals. In the CPU, counting input signals with higher scan frequencies can also be achieved using high-speed counter instructions. 1. High-Speed ​​Counter Instructions High-speed counter instructions include: the high-counter definition instruction HDEF and the high-speed counting execution instruction HSC, as shown in the table below. (1) Define the high-speed counter instruction HDEF. The HDEF instruction selects a working mode for a high-speed counter to be used. Each high-speed counter must be defined using the HDEF instruction before use, and it can only be used once. It has two input terminals: HSC is the number of the high-speed counter to be used, the data type is byte, and the data range is a constant of 0~5, corresponding to HC0~HC5 respectively; MODE is the working mode of high-speed counting, the data type is byte, and the data range is a constant of 0~11, corresponding to 12 working modes respectively. When the input enable EN is valid, the working mode MODE is defined for the specified high-speed counter HSC. (2) Execute the high-speed counting instruction HSC. The HSC instruction determines the control mode and working state based on the special relays related to the high-speed counter, makes the high-speed counter settings effective, and executes the counting operation according to the working mode of the instruction. It has one data input terminal N: N is the number of the high-speed counter, the data type is byte, and the data range is a constant of 0~5, corresponding to high-speed counters HC0~HC5 respectively. When the input enable EN is valid, the high-speed counter N is started. 2. The input terminals of the high-speed counter are not user-defined like ordinary input terminals, but are input signals specified by the system. Each high-speed counter has dedicated input points for the pulse input terminals it supports, direction control, reset and start, and completes the predetermined operation through comparison or interrupt. The dedicated input points of each high-speed counter are shown in the table below: 3. Status byte of the high-speed counter The system provides a status byte in the special register area SMB for each high-speed counter. In order to monitor the working status of the high-speed counter and execute the interrupt event referenced by the high-speed counter, its format is shown in the table below: The status bit of the status byte is only valid when the interrupt program of the high-speed counter is executed. 4. Working modes of the high- speed counter There are 12 different working modes (0`~11) of the high-speed counter, which are divided into 4 categories. Each high-speed counter has multiple working modes, which can be selected by programming using the high-speed counter definition instruction HDEF. (1) Working modes of each high-speed counter a. The high-speed counter HC0 is a general-purpose increment and decrement counter with 8 modes. Different working modes can be selected by programming. The working modes of HC0 are shown in the table below: b. The high-speed counter HC1 has 12 modes, as shown in the table below: c. The high-speed counter HC2 has 12 modes, as shown in the table below: d. The high-speed counter HC3 has one mode, as shown in the table below: e. The high-speed counter HC4 has 8 modes, as shown in the table below: f. The high-speed counter HC5 has one mode, as shown in the table below: 5. The high-speed counter control byte system assigns a special register SMB as the control word for each high-speed counter. The operating mode of the high-speed counter can also be determined by setting the control byte. Before executing the HSC instruction, the UN200 CPU first checks the control byte associated with each high-speed counter. The control byte sets the effective levels of the start and reset input signals, the counting multiplier of the quadrature counter, the effective level of the internally controlled counting direction, whether changing the counting direction is allowed, whether updating the set value is allowed, whether updating the current value is allowed, and whether executing high-speed counting instructions is allowed. Explanation: (1) Among the 12 operating modes of the high-speed counter, modes 0, 3, 6 and 9 are counters without either a start input or a reset input; modes 1, 4, 7 and 10 are counters with only a reset input and no start input; modes 2, 5, 8 and 11 are counters with both a start input and a reset input. (2) When the start input is valid, the counter is allowed to count; when the start input is invalid, the current value of the counter remains unchanged; when the reset input is valid, the current value register of the counter is cleared; when the start input is invalid and the reset input is valid, the effect of the reset is ignored and the current value of the counter remains unchanged; when the reset input remains valid and the start input becomes valid, the current value register of the counter is cleared. (3) In the UN200 CPU, the system defaults to both the reset input and the start input being active high, and the quadrature counter is 4 times the frequency. If you want to change the system's default settings, you need to set bits 0, 1, and 2 of the special relays as shown in the table above. The counting direction control, setpoint and current value control, and high-speed counting execution control of each high-speed counter are determined by bits 3 to 7 of the relevant control bytes in Table 4-22. 6. Current Value Register and Setpoint Register of High-Speed ​​Counters Each high-speed counter has one 32-bit passed value register HC0-HC5, and also one 32-bit current value register and one 32-bit setpoint register. Both the current value and setpoint are signed integers. To load a new current value and setpoint into the high-speed counter, the current value and setpoint must first be loaded into the special registers listed in the table as double-word data types. Then, the HSC instruction is executed to transfer the new value to the high-speed counter. 7. Initialization of the high-speed counter Since the HDEF instruction of the high-speed counter can only be executed once after entering RUN mode, in order to reduce program running time and optimize program structure, it is generally initialized in the form of a subroutine. The following uses HC2 as an example to introduce the initialization steps of each working mode of the high-speed counter. (1) Use SM0.1 to call an initialization subroutine. (2) In the initialization subroutine, load the control word into SMB47 as needed. For example, SMB47=16#F8, which means: allow writing a new current value, allow writing a new set value, the counting direction is forward counting, and the start and reset signals are active high. (3) Execute the HDEF instruction, the input parameters are: HSC terminal is 2 (select high-speed counter No. 2), MODE terminal is 0/1/2 (corresponding to working mode 0, mode 1, mode 2). (4) Load the desired current technical value into SMD58 (loading 0 can clear the counter). 5. Load the desired set value into SMD62. (5) If you want to capture an interrupt event where the current value equals the set value, write an interrupt service routine associated with interrupt event number 16. (6) If you want to capture an external reset interrupt event, write an interrupt service routine associated with interrupt event number 18. (7) Execute the ENI instruction . (8) Execute the HSC instruction. (9) Exit the initialization subroutine. 8. Example of high-speed counter application. A product packaging production line uses a high-speed counter to accumulate and package products. When 1000 products are detected, the packaging machine is automatically started for packaging. The counting direction can be controlled by an external signal. Design steps: (1) Select a high-speed counter and determine the working mode . In this example, the selected high-speed counter is HC0. Since the technical direction is required to be controlled by an external signal and it does not need a reset signal input, the working mode is determined to be mode 3. The interrupt event where the current value equals the set value is used. The interrupt event number is 12. Start the packaging machine working subroutine. The initialization of the high-speed counter is done using a subroutine. (2) Use SM0.1 to call the high-speed counter initialization subroutine. The subroutine number is SBR_0. (3) Write the control word SMB37=16#F8 to SMB37. (4) Execute the HDEF instruction, input parameters: HSC is 0, MODE is 3. (5) Write the current value to SMD38, SMD38=0. (6) Write the set value to SMD42. SMD42=1000. (7) Execute the interrupt connection establishment instruction ATCH, input parameters: INT is INT-0, EVNT is 12. (8) Write the interrupt service routine INT0, in this example, it calls the packaging machine control subroutine, the subroutine number is SBR-1. (9 ) Execute the global interrupt enable instruction ENI. (10) Execute the HSC instruction to program the high-speed counter and put it into operation. The following is a program example: MAIN:      Subroutines and interrupt routines were not written. This concludes the detailed explanation of the high-speed counting function of the EVE UN200 CPU. We hope this article will be helpful for your understanding and application of high-speed counting.