Abstract : This paper conducts an in-depth study of the main circuit and peripheral circuits of a parallel active power filter (APF). The selection of switching devices and the design of the buffer circuit in the main circuit are discussed in detail. Using a combination of theoretical analysis and simulation experiments, methods for selecting the DC bus voltage, DC bus capacitance, and AC side filter inductance are presented. Based on the above analysis methods, the specific device selection for the main circuit and the detailed design parameters of the peripheral circuits of the parallel APF are derived.
Keywords : Parallel active power filter peripheral circuit
1 Introduction
An Active Power Filter (APF) is a novel power electronic device that dynamically suppresses harmonics and compensates for reactive power. It can compensate for harmonics and reactive power with varying frequencies and amplitudes, overcoming the shortcomings of passive filters and achieving better compensation characteristics, making it an ideal harmonic compensation device. Compared to passive filters, APFs offer high controllability and fast response. Currently, commonly used APF main circuits can be divided into four-phase converter circuits and three-phase converter circuits. Three-phase three-wire APFs have been successfully applied in some industrial products, while the topology of three-phase four-wire APFs, although introduced as early as the 1980s, is still in the research stage in practical systems, with many problems requiring further study and resolution. However, the proportion of harmonics generated by three-phase four-wire systems in the entire power grid is increasing, making the research on how to utilize APFs for harmonic and reactive power compensation in three-phase four-wire systems of great significance.
2APF Main Circuit Mathematical Model
The parallel three-phase four-wire active power filter circuit is shown in Figure 1. The DC side neutral line is connected to the system center line. Assume that the DC voltage values of the upper and lower half-bridge arms are equal, and define the DC side upper and lower capacitor voltages as follows. Since the system DC side neutral line is connected to the system center line, when a phase bridge arm is conducting, the voltage at the midpoint of that phase bridge arm is ; if the lower half-bridge arm of that phase is conducting, the voltage at the midpoint of that phase bridge arm is . Based on this, the switching function can be defined as shown in equation (1).
The voltage at the midpoint of the bridge arm is given by equation (2).
Figure 1. Connection diagram of the main circuit of a three-phase four-wire APF
The switching parameters of the three-dimensional spatial voltage vector can be listed from (4) and (5) as shown in Table 1.
Table 1. Parameters of Three-Dimensional Space Voltage Vector Switch
3 Power Module Selection
To simplify and improve the reliability of the power circuit, an Intelligent Power Module (IPM) was selected as the main power circuit for the two-phase inverter. The IPM integrates logic, control, detection, and protection circuits, making it easy to use. This not only reduces the system size and development time but also significantly enhances system reliability, aligning with the current development trend of power devices. When selecting an IPM, the DC bus voltage it can withstand must be considered. The maximum voltage that the power switching transistor can withstand is the DC output peak value; knowing the DC output peak value allows for its calculation. When selecting the power transistor's current rating, considering the presence of harmonic components in the input current, a certain safety margin must be allowed; therefore, the actual peak current is generally taken as approximately three times the design value. This control system uses a Mitsubishi PM100RSE120 IPM with a larger capacity. This model of IPM can withstand a DC voltage of 1200V and a rated current of 100A.
3.1 DC Side Voltage Calculation
When an active power filter is operating normally, its output compensation current exhibits a sawtooth wave pattern on both sides of the command current, following its variation. Based on the main circuit analysis of the active power filter, for phase a...
When ia It is known that in order to control the current variation trend, the DC bus voltage must be greater than three times the peak value of the AC power supply phase voltage; otherwise, the compensation current will not change as required. Different DC bus voltage values will result in different compensation effects depending on the modulation method. This paper focuses on a voltage feedforward current decoupling control method based on SVPWM modulation, selecting 950V as the DC bus voltage. 3.2 Calculation of DC-side capacitor value The DC-side capacitor buffers the energy pulsations of the compensation current between the AC power supply and the active power filter, which are the main cause of DC-side voltage fluctuations. If the capacitor value is too small, the DC-side voltage of the main circuit will fluctuate too much, affecting the compensation effect of the active power filter; if the capacitor value is too large, the dynamic response of the DC-side voltage of the main circuit will be slower, and the size and cost of the capacitor will also increase. If the voltage setting of the DC-side capacitor in the main circuit is , then the energy stored in the capacitor is . Since it is generated by compensation current, its specific value varies depending on the harmonic source and compensation requirements. In addition, there is another method for calculating the DC-side capacitor of the main circuit. Considering that the DC-side capacitor of the main circuit is always in a charging and discharging state when the active power filter is working normally, assuming that the capacitor is always in a charging or discharging state within a certain PWM cycle, then we have: Therefore, once the compensation capacity of the device and the allowable DC bus voltage fluctuation value are determined, the bus capacitor capacity can be determined. It should be noted that the calculated capacitance is obtained under ideal conditions; a certain margin must be allowed when actually selecting the bus capacitor capacity. 3.3 Selection of AC-side reactor The primary function of the AC-side inductor is to convert the changing voltage into the actual compensation current. Microscopically, the waveform of the compensation circuit is a sawtooth wave oscillating up and down along both sides of the command current. Therefore, if the inductance value is too small, the amplitude of the sawtooth wave will increase, thereby increasing the ripple component in the compensation current. This, in turn, increases the capacity of the subsequent high-pass filter, increasing the cost of the passive compensator and the overall system size. Conversely, if the inductance value is too large, the compensation current cannot track the command current in real time and will not provide compensation. Taking phase a as an example, if the active filter operates for a sufficiently long time, the average effect of the AC voltage will be 0, while the average value of the current is 4/9. From this, we can conclude that: The choice of the minimum inductance value depends on the allowable magnitude of switching harmonics. This value must be limited to a certain range when selecting the inductor. Assuming the fluctuation rate of the source filter output current is δ, then: In the formula, represents the harmonic current amplitude caused by the active filter switching, represents the output current amplitude of the active filter, and represents the allowable output current fluctuation rate. From Equation 28, it can be seen that the ripple current amplitude at the output current amplitude point is: Based on the above analysis, the range of values for L can be determined to be 1.1mH. 3.2mH. The inductance of the main circuit of this system was determined through simulation studies based on calculated values and practical applications, and finally, L=1.7mH was selected. 3.4 Control System Hardware Design This system is based on the Texas Instruments (TI) TMS320F2812 digital signal processor (DSP) chip, supplemented by detection circuits and other peripheral control and drive circuits. The hardware block diagram of the controller is shown in Figure 2. The detected signals are isolated, filtered, and conditioned before being connected to the DSP's AD port, converted, and stored in memory. Finally, the DSP performs all digital signal processing, including voltage and current acquisition and RMS value calculation, harmonic and reactive current calculation, and PWM signal generation. 3.5 Voltage Phase Detection Circuit The ip and iq detection method uses a sine wave and a cosine wave, both of which have the same phase as the phase a voltage signal. Therefore, before obtaining these two values using a lookup table in the DSP chip, the phase of the phase a voltage signal must first be obtained through hardware circuitry, as shown in Figure 3. The zero-crossing detection circuit schematic is shown in Figure 4. In this design, a 220V/8.5V synchronous transformer is used to convert the phase a voltage into a low-voltage signal. This signal then passes through a filter circuit, a zero-crossing comparator circuit, and optocoupler isolation to become a 0-3.3V square wave signal, which is then fed into the DSP. The filter circuit, composed of adjustable resistors RW1 and C1, eliminates the influence of higher harmonics. The zero-crossing comparator circuit, consisting of an LM339 and resistors, uses R3 and R4 to form a hysteresis loop, preventing ground interference that could cause multiple zero-crossings within a single grid cycle, thus affecting the control signal. The optocoupler isolation circuit further refines the PHA square wave signal, while simultaneously isolating the analog signal from the digital signal fed into the DSP. 3.6 Phase-locked loop frequency multiplier circuit Because the frequency of the power system is not fixed but fluctuates around 50Hz, using timer interrupts to provide a reference for analog signal sampling will inevitably cause significant errors. To adapt to this situation, the DSP's periodic timing is changed to frequency counting. As long as this frequency is a multiple of the mains power supply frequency, each multiple of the pulse represents a fixed electrical angle. If the phase of this multiple of the pulse train is strictly locked with the mains power supply frequency, this scheme can eliminate the triggering error caused by the instability of the power grid frequency in principle. Figure 2 Hardware structure block diagram of the controller Figure 3a Phase voltage phase detection circuit Figure 4. Schematic diagram of zero-crossing detection circuit Figure 5 Phase-locked frequency multiplier circuit Figure 6 Schematic diagram of analog signal acquisition circuit 2. Implementation of phase-locked loop frequency multiplier circuit The phase-locked loop (PLL) frequency multiplier circuit is shown in Figure 5. In the figure, C3, R8, and RW11 determine the center oscillation frequency and phase-locked range of the CD4046. The low-pass filter parameters are related to the input signal frequency; the lower the cutoff frequency of the low-pass filter, the smaller the fluctuation of the PLL output frequency, but the slower its tracking speed. Therefore, its parameters should be determined according to the actual grid frequency change rate and the required PLL speed. In this design, the locking frequency range is set to 45Hz～55Hz, the center frequency is 50Hz, and the multiplication factor is 256. The square wave signal XIN generated by the zero-crossing detection circuit and synchronized with the phase a voltage is sent to the SIGIN terminal of the CD4046. The CD4046 outputs the multiplied frequency signal VCOUT, which is sent to the frequency divider CD4040. After being divided by 256, it is sent to the VCOIN terminal of the CD4046. The CD4046 contains a phase detector and a voltage-controlled oscillator (VCOIN). The SIGIN and VCOIN input signals are fed into the phase detector, which compares the phase of the two input signals and outputs a voltage proportional to the phase error. The phase detector output is then fed into a low-pass filter composed of R9 and C4 to filter out high-frequency components. Its output is then fed into the VCOIN, which outputs a square wave signal with a frequency proportional to the input DC voltage. Thus, the CD4046 and CD4040 form a closed-loop phase-locked loop frequency multiplier circuit. The output signal at pin 4 is 256 times the input signal XIN at pin 14. 3.6 Current Signal Acquisition and Conditioning Circuit The measured quantity in this system contains high-order harmonic components, therefore the detection circuit places high demands on the performance of the current transformer. High-performance Hall elements are used in the design. The TBC100LA Hall current sensor is used for current detection. The primary and secondary windings of the TBC-LA100 current sensor are insulated, and it can be used to measure DC, AC, and pulse currents, with a rated input RMS current of 100A. The analog signal acquisition circuit is shown in Figure 6: by adjusting resistors RW18 and RW20, the measured current value is adjusted to between 0V and 3.3V, thus meeting the DSP's input signal requirements. 4 Results Analysis Figure 7 shows the currents of phases A and B before compensation, with phase A having a larger amplitude due to the additional 8Ω resistor. Figure 8 shows the currents of phases A and B after compensation, where only harmonic components are compensated but zero-sequence components are not. Figure 9 shows the current waveforms of phases A and B after harmonic and zero-sequence compensation, and the neutral current is also partially compensated. In Figure 10, the total DC voltage and the voltages of the upper and lower capacitors are well stabilized. Figure 7 shows the currents of phases A and B before compensation. Figure 8 shows the current after compensation for phases A and B. Figure 9 shows the currents after compensation for phases A and B (compensated zero sequence). Figure 10 DC bus voltage and upper and lower capacitor voltage values 5. Conclusion Active power filters are widely recognized as the most effective means of controlling power grid harmonics and reactive power pollution, and improving power quality. Compared with passive filters, active power filters have unparalleled advantages, thus becoming a research hotspot both domestically and internationally. However, the application of active power filters in China is still immature, and they remain secondary in practical applications compared to passive filters, requiring further research and improvement. Therefore, this paper conducts an in-depth study of active power filters based on a space vector predictive current control strategy. The paper first discusses harmonic detection methods based on instantaneous reactive power theory, and verifies through simulation that this detection method has better detection performance for power grid distortion in both three-phase three-wire and three-phase four-wire systems. The hardware circuit design of the three-phase four-wire system is described in detail. Experimental results prove the correctness of the analysis. References [1] Ling Qing. Research on Control Method of Three-Phase Parallel Active Power Filter [D]. Xi'an Jiaotong University, 2005 [2] Zhou Guoliang. Implementation of Active Power Filter Device Based on DSP [D]. North China Electric Power University (Baoding), 2004 [3]SasakiH,MachidaT.Anewmethodtoeliminateacharmoniccurrentsbymagneticcompensationonbasicdesign.IEEETransPowerApp&Syst,1971,90(5):2009~2019 [4] Zhang Chongwei, Zhang Xing, PWM Rectifier and Its Control [M], Beijing: China Machine Press, October 2003. [5] Zhuo Fang, Yang Jun, Hu Junfei, Wang Zhaoan, Experimental study on parallel active power filter for three-phase four-wire system [J], Power Electronics Technology, 1999.12.16~18 [6] Yuan Wenhua. Design and Research of Three-Phase PWM Rectifier [D]. Xuzhou: China University of Mining and Technology, 2007.6 About the Author Lü Xianxin (1986-) is currently employed at Harbin Jiuzhou Electric Co., Ltd., where he is mainly engaged in the design of DC systems for power plants, smart grid systems, and integrated power supply design and development. Zhou Jiaqi (1983-) is a male with a master's degree. He currently works at Harbin Jiuzhou Electric Co., Ltd. as an intermediate engineer. He is mainly engaged in the research and development of new energy power generation technology and reactive power compensation technology.
