For applications requiring switching between multiple FPGA configuration streams, Xilinx has proposed a solution called SystemACE. It uses a CF (CompactFlash) memory card to replace the configuration PROM, and a dedicated ACE control chip to read and write the CF card. The host computer software generates a dedicated ACE file and downloads it to the CF memory card. After power-on, the ACE control chip enables switching between different configuration streams.
SystemACE's solution requires the purchase of CF memory cards and dedicated ACE control chips, increasing system setup costs and space consumption. Furthermore, this solution only supports switching between a maximum of eight configuration files, rendering it ineffective when dealing with more. Developing an alternative to SystemACE necessitates selecting a more suitable reprogrammable memory and an appropriate transmission protocol interface for downloading the configuration stream. Downloading the configuration stream via serial or parallel ports is too slow to meet the application's need for fast downloading; downloading via USB requires a dedicated control chip, increasing system design costs.
This paper presents an FPGA multi-configuration solution that utilizes a large-capacity NOR Flash memory to store configuration streams and leverages the JTAG interface to download the configuration streams. Compared to the SystemACE solution, this solution not only enables faster downloading of multiple configuration streams but also offers higher configuration speed and lower implementation cost.
1. Design of JTAG Interface Module
To write the configuration stream to the Flash memory, the host computer software connects to the JTAG interface module via a JTAG download cable. The JTAG interface module receives JTAG signals sent by the host computer software, extracts the JTAG commands and corresponding data, and generates erase and write signals for the Flash memory. Based on the IEEE 1149.1-2001 standard and the erasure-before-write characteristic of NOR Flash memory, the specific execution flow of the host computer software is designed as shown in Figure 1. Simultaneously, to complete the erasure and write operations of the Flash memory, this paper defines a series of custom JTAG commands in the software design, as shown in brackets in Figure 1. This paper specifies that the size of one data frame is 4096 bits.
Figure 1. Host computer software programming process for Flash memory
After receiving the JTAG signal via an external pin, the JTAG interface module must include a TAP (Test Access Port) controller to extract JTAG instructions and data. The TAP controller is a 16-state state machine; state transitions are controlled by changes in the TMS over the rising edge of the TCK. In specific states, JTAG instructions and data are stored in the instruction register (IRInstructionRegister) and data register (DRDataRegister), respectively. The interpretation of instructions received from the host computer software by the JTAG interface module is shown in Table 1.
Table 1 Explanation of JTAG Commands
2. Flash Controller and FPGA Device Configuration Module Design
2.1 Flash Controller Design
Both programming and configuring FPGA devices using Flash memory require operations on the Flash memory. Therefore, a controller module needs to be designed to generate control instructions for the Flash memory. The Flash controller's functions are: responding to erase, write, and read commands, and generating corresponding timing sequences based on the commands to perform operations on the Flash memory.
To store multiple configuration files in a single Flash memory block, the Flash can be divided into multiple regions based on the size of the configuration files. Thus, for a specific configuration file, the scope of input commands should be limited to the region where the configuration file is stored. Therefore, when erasing a configuration file, a block erase method should be used, rather than a full-block erase method.
To ensure timely writing of a configuration bitstream frame into the Flash memory, the Flash memory programming time must be less than the waiting time after the FPGM instruction is executed. Calculations based on reference data in the Flash memory datasheet revealed that using the ordinary programming method to write a configuration bitstream frame takes longer than the waiting time, while using the write-buffered programming method takes less time. Therefore, the write-buffered programming method must be selected for writing to the Flash memory.
The command and data translation between the JTAG interface and the Flash controller is handled by the programming control module in the reverse-compatible JTAG controller. It receives erase or write commands from the JTAG interface, translates them, and generates the necessary commands, addresses, and data for the Flash controller. Since the data written to the Flash memory in a single write buffer is less than the size of a configuration bitstream frame, upon receiving a write command, the programming control module, in conjunction with the write command and the corresponding operation address, sends a configuration bitstream frame from the buffer to the Flash controller in multiple steps.
2.2 FPGA Device Configuration Module Design
There are four configuration modes for Virtex series FPGA devices: serial master mode, serial slave mode, parallel slave mode, and boundary scan mode. The master mode uses an internal oscillator to provide the clock, while the slave mode and boundary scan mode use an externally provided clock. After the FPGA device is powered on and initialized, the configuration module sends the configuration code stream and configuration clock to the FPGA to configure the FPGA device. Because the faster the configuration speed, the shorter the waiting time before the FPGA device starts working, this scheme selects the fastest parallel slave mode [6]. Figure 2 is the timing diagram of the parallel slave mode. The data (DATA[7:0]) must meet the constraints of setup time (Tsu) and hold time (Th). The steps of the FPGA device configuration module to configure the FPGA device are as follows:
1. When the FPGA device configuration module detects that the INIT pin signal has gone high, it indicates that the automatic initialization of the FPGA device has been completed after power-on. The configuration module then sends a read command to the Flash controller.
2. After receiving the configuration code stream returned by the Flash controller, the configuration module sends an 8-bit configuration code stream to the FPGA device on each rising edge of the clock.
3. The configuration module detects that the DONE pin signal goes high, indicating that the FPGA device has been configured and the configuration process is over.
Figure 2. Timing diagram of parallel slave mode
4. Since the time from sending a read command to the Flash controller to the Flash controller returning the configuration bitstream is greater than one cycle, and the bit width of the returned data is greater than the data bit width in parallel slave mode, the configuration bitstream must be converted in bit width first. At the same time, to ensure that an 8-bit configuration bitstream is sent out on each rising edge of CCLK, CCLK must be appropriately frequency-divided.
Design and implementation of 3 schemes
All control logic in this solution is implemented using a single Xilinx Spartan II series XC2S200 FPGA. Spansion's NOR Flash memory (model S29GL512N, 512Mb) is used to store the configuration file. The overall system block diagram is shown in Figure 3. The host computer software includes a Flash programming tool and a serial port tool. When programming the configuration file, the Flash programming tool transmits JTAG commands and configuration code streams to the control FPGA via a JTAG download cable. Simultaneously, the serial port tool sends the configuration file address to the control FPGA via a serial port, completing the switching of the configuration file storage area. When configuring the FPGA, the serial port tool sends the configuration file address and reconfiguration signal to the control FPGA via a serial port, completing the switching of the configuration file. If there are too many configuration files in a practical application, a Flash memory array can be used to increase the storage depth.
Figure 3 System Overall Block Diagram
3.1 FPGA Implementation of the Design
The logic control functions implemented by the FPGA include communication with the host computer software iMPACT and serial port tools, Flash programming, and FPGA device configuration. Based on a modular design approach, the specific functions are decomposed into multiple modules, as shown in Figure 3. The subscripts on the data and address channels represent their channel widths. The functions of each module are as follows:
1. The RS232 interface module receives the configuration file address and reconfiguration signal from the serial port tool. After decoding the configuration file address, the starting address for various operations on the Flash memory is obtained, and the reconfiguration signal is used to trigger the switching of the FPGA configuration file.
2. The JTAG module includes a JTAG interface module, a data buffer module, and a programming control module. After receiving JTAG commands and data from the JTAG download line, the JTAG interface sends an erase or programmable signal to the programming control module if the command is FERASE or FPGM. If the command is FDATA0, it receives serial data from the TDI and stores it in the data buffer module. The data buffer module utilizes on-chip BRAM and can store one frame of configuration code stream. Upon receiving an erase signal, the programming control module generates an erase command and operation address and sends them to the status selection module. Upon receiving a programmable signal, it reads the configuration code stream from the data buffer module, generates a write command and operation address, sends them to the status selection module, and sends the operation data directly to the Flash controller.
3. After receiving the start address and reconfiguration signal from the RS232 interface module, the FPGA configuration module first sends an initialization signal to the FPGA device to be configured. After the initialization is completed, it continuously sends read commands and operation addresses to the status selection module and uses the configuration code stream returned from the Flash controller to configure the FPGA device.
4. The status selection module selects the input of the Flash controller based on the external programming/configuration signal, thereby determining whether the FPGA is currently in the programming Flash memory state or the configuration FPGA device state. If it is "0", the command and address generated by the programming control module are input, controlling the FPGA to be in the programming Flash memory state; if it is "1", the command and address generated by the configuration control module are input, controlling the FPGA to be in the configuration FPGA device state.
The Flash controller responds to these input commands, operation addresses, and data, generates Flash memory control timing corresponding to the commands, and returns data output to the Flash memory.
3.2 Actual Performance Testing
In programming mode, the system can communicate normally with the host computer software via the JTAG interface and serial port. After loading the appropriate configuration file, it can complete the erase and write operations of the Flash memory, with a measured writing speed of 160Kb. When multiple configuration files need to be written, the configuration file address can be sent via a serial port tool to operate on different Flash spaces.
In configuration mode, taking the Virtex XCV1000 FPGA as the configuration target, its configuration file size is approximately 5.84Mb. A measured configuration time of 60ms indicates a configuration speed of approximately 97Mb/s, significantly higher than the SystemACE solution's 30Mb/s. To switch between different configuration files, the configuration file address and reconfiguration signal can be sent via a serial port tool, enabling real-time switching between multiple configuration files.
Conclusion
This paper analyzes the advantages and disadvantages of various transmission protocol interfaces and the SystemACE multi-configuration solution. Based on practical application requirements, it proposes an FPGA multi-configuration system solution based on high-capacity NOR Flash and utilizing the JTAG interface to complete configuration stream download. This system uses Flash memory instead of PROM or CF card for configuration, saving hardware costs and space. Theoretically, it can support an unlimited number of configuration file switching, and the FPGA configuration speed is more than three times that of the SystemACE solution.
