1 Introduction
The EnDat interface is a digital, full-duplex, synchronous serial data transmission protocol designed by HEIDENHAIN specifically for encoders . It boasts advantages such as high transmission speed, powerful functionality, simple wiring, and strong anti-interference capabilities, making it a universal interface for data transmission between encoders and linear scales. Because it uses serial transmission, only four signal lines are needed. Data information is transmitted synchronously under the clock excitation of subsequent electronic equipment. The data type (position value, parameters, diagnostic information, etc.) is determined by the mode command sent to the encoder by the subsequent electronic equipment. The encoder uses natural binary, cyclic binary (Gray code), or PRC code to photoelectrically convert the physical lines on the code disk, converting the rotation angle of the connecting shaft into a corresponding electrical pulse sequence and outputting it as a digital quantity. It features small size, high precision, digital interface, and absolute positioning, and is widely used in rotary tables, robots, CNC machine tools, and high-precision servo systems, among other fields.
2. Introduction to EnDat Interface
2.1 Features of the EnDat Interface
(1) High performance and low cost: The universal interface is suitable for all incremental and absolute encoders , with more economical power consumption, small size and compact connection, quick system configuration, and zero point can be floated according to the bias value.
(2) Better signal quality: Special optimizations inside the encoder improve system accuracy and provide better contour accuracy for CNC systems.
(3) Better usability: Automatic system configuration function; digital signals improve system reliability; monitoring and diagnostic information is beneficial to system security; redundancy code verification is beneficial to reliable signal transmission.
(4) Improved system security: two independent location information and error information bits, data verification and response.
(5) Applicable to advanced technology development: (high resolution, short control cycle, fastest 16M clock, safe design concept) Applicable to direct drive technology.
2.2 Improvement of EnDa2.2 Encoder Performance
(1) Location value and additional information can be transmitted simultaneously: the type of additional information can be selected by the storage address selection code.
(2) The encoder data storage area includes encoder manufacturer parameters, OEM manufacturer parameters, operating parameters, and operating status, which facilitates the system to configure parameters.
(3) The EnDa2.2 encoder realizes all-digital transmission. The processing of incremental signals is completed inside the encoder (built-in 14-bit subdivision), which improves the quality and reliability of signal transmission and can achieve higher resolution.
(4) Monitoring and diagnostic functions, alarm conditions include: light source failure, insufficient signal amplitude, position calculation error, operating voltage too low or too high, current consumption too high, etc.; warning signals are provided when some of the encoder's limit values are approached or exceeded.
(5) Wider voltage range (3.6 to 14V) and transmission rate (16M).
2.3 Time-series and OEM data storage
During each frame of synchronous data transmission, a data packet is sent. The transmission cycle begins with the first falling edge of the clock, where measured values are saved and position values are calculated. After two clock pulses (2T), the subsequent electronic device sends the mode command "Encoder Transmit Position Value" (with or without additional information). After the absolute position value is calculated (see Figure 2), the encoder transmits data to the subsequent electronic device starting from the start bit. The subsequent error bits F1 and F2 (existing only in the EnDa2.2 command) are group signals serving all monitoring functions and fault monitoring. Their generation is independent and they are used to indicate encoder faults that may lead to incorrect position information. The exact cause of the fault is stored in the "Operating Status" memory area, which can be queried by the subsequent electronic device.
Starting with the least significant bit, the absolute position value is transmitted, and the data length is determined by the type of encoder used. The number of clock pulses required to transmit the position value is stored in the encoder manufacturer's specifications. The transmission of the position value data ends with a cyclic redundancy check code.
If the location value includes additional information, it is followed by additional information 1 and 2, each ending with a CRC (see Figure 3). The content of the additional information is determined by the selected memory address and is then transmitted in subsequent sampling periods. This information continues to be transmitted in subsequent transmissions until a new memory area is selected. At the end of the data word, the clock signal must be set high. After 10–30 μs or 1.25–3.75 μs (EnDat programmable recovery time tm), the data line returns to low, and then new data transmission can begin on a new clock signal.
Meanwhile, the encoder provides different storage areas for parameters, which can be read by subsequent electronic equipment. These areas can be written to by the encoder manufacturer, OEM, and even end users. Some specific areas are write-protected. Different encoder series support different OEM storage areas and different address ranges. Therefore, each encoder must read the allocation information of the OEM storage area. For this reason, subsequent electronic circuitry should be programmed based on relative addresses, not absolute addresses.
Circuit design scheme for subsequent electronic devices with 3EnDat interface
The fully digital AC servo system uses a TMS320F2812 as the controller to implement position, speed, and current loops, as well as SVPWM, voltage, and current sampling functions. Furthermore, an Altera Cyclone series FPGA (EP1C6Q240C8) is used to implement the encoder interface and decoding logic. Simultaneously, a 128B dual-port RAM is implemented within the FPGA, enabling data transmission with the DSP via a bus. The functional block diagram is shown in Figure 4.
The FPGA is internally divided into five parts: a clock generation module, a transmitting module, a receiving module, a dual-port RAM module, and a transmitting enable module. First, the clock generation module generates a square wave signal with a period of 0.5μs, named CLOCK, which serves as the communication synchronization clock signal. On each rising edge of the CLOCK clock, the counter variable COUNT increments by 1, with an initial value of 0. When the transmitting enable module detects a COUNT value of 3, it indicates that the encoder has finished saving the position value. The transmitting enable module then activates the SENT_EN signal, and the transmitting module begins sending 6-bit mode instructions. When a COUNT value of 9 is detected, COUNT stops counting on each rising edge of the clock, data transmission stops, and the RECEIVE_EN receiving enable signal is activated, thus enabling the receiving module. The receiving module begins detecting the rising edge of the data input signal. Once the rising edge arrives, it indicates that the data start bit s has been received. It then starts counting on each rising edge of the clock, saving the position value on each rising edge of the clock signal until the detected COUNT value is 39. At this point, data reception stops, and the receiving module writes the position value to be saved to port A of the dual-port RAM module, thus ending one communication process between the FPGA and the encoder. Since each communication time is strictly fixed, let's assume the system clock is 2MHz. The FPGA is the caller. When the falling edge of the clock arrives, the encoder needs 2 clock cycles to save the position value, and sending the 6-bit "request data" control word "000111" to the encoder takes 6 clock cycles. The encoder sends 1 start bit, 2 "error bits," 23 position bits, and 5 CRC check bits to the FPGA, taking 31 clock cycles, for a total of 39 clock cycles. Therefore, each communication takes 19.5μs, and the specific data bit to be transmitted at each moment is also strictly determined. Therefore, a time-based design method is adopted (see Figure 5).
A 128B dual-port RAM space is implemented inside the FPGA. Port A has 8 data lines and 7 address lines for communication with the encoder, while Port B has 16 data lines and 7 address lines for communication with the DSP. Because the TMS320F2812 is a 16-bit DSP, data transfer with the RAM in the FPGA is extremely convenient. The DSP sends a valid "BEGIN" signal in each current loop cycle. After 19.5μs, the code disk signal receiving module stores the received data in Port A of the FPGA's internal dual-port RAM, arranging it sequentially into 16-bit data. Then, it sends an "END" signal to the DSP, indicating the end of a communication cycle. Upon receiving the interrupt, the DSP reads the data from Port B of the FPGA's dual-port RAM, completing one communication cycle.
The FPGA development utilizes Xilinx's ISE integrated environment, with Verilog HDL as the hardware description language. Figure 6 shows the program flowchart.
4. Conclusion
This paper designs an FPGA-based encoder interface for communication between the encoder and the servo driver DSP processor, and includes error correction functions such as CRC check. The paper presents the hardware connection and FPGA programming flow, enabling accurate reading of the magnetic pole positions of a permanent magnet synchronous AC motor.
