Selecting devices for industrial systems requires consideration of several factors, including performance, cost of engineering changes, time to market, personnel skills, the possibility of reusing existing IP/libraries, cost of field upgrades, and low power consumption and low cost.
Recent developments in the industrial market have driven demand for highly integrated, high-performance, and low-power FPGA devices. Designers prefer network communication over point-to-point communication, which may require additional controllers for communication, indirectly increasing BOM costs, board size, and associated NRE (one-time engineering costs).
Total cost of ownership (TCO) is used to analyze and estimate the life-cycle costs of an acquisition. It is an extended set of all design-related direct and indirect costs, including engineering costs, installation and maintenance costs, bill of materials (BOM) costs, and non-renewal (NRE) costs. By considering system-level factors, it is possible to minimize TCO, thereby leading to sustainable long-term profitability.
Microsemi offers SmartFusion2 SoCFPGA devices with a hard-core ARM Cortex-M3 microcontroller and integrated IP, packaged in a cost-optimized manner to reduce BOM and board size. These devices feature low power consumption and a wide temperature range, enabling reliable operation in extreme conditions without cooling fans. The SmartFusion2 SoCFPGA architecture integrates a hard-core ARM Cortex-M3 IP with the FPGA architecture, enabling greater design flexibility and faster time-to-market. Microsemi provides an ecosystem of multi-axis motor control reference designs and IP for motor control algorithm development, making it easier to transition from multi-processor solutions to single-device solutions (i.e., SoCFPGAs).
Factors affecting TCO
The following are some factors that affect the total cost of ownership (TCO) of a system.
(1) Long life cycle. FPGAs can be reprogrammed after field deployment, which extends the product life cycle, allowing designers to focus on new product development and achieve faster time to market.
(2) Bill of Materials (BOM). Microsemi's flash memory-based FPGAs do not require a PROM or flash MCU to load the FPGA upon power-up; they are zero-level non-volatile/instant-on devices. Unlike SRAM-based FPGAs, Microsemi's flash memory-based FPGAs do not require an additional power-up monitor because the flash switches do not change with voltage.
(3) Time to Market. Intense competition among OEMs necessitates greater product differentiation and faster time to market. Proven IP modules can significantly shorten design time. Several IP modules are already available for building industrial solutions, with more under development. Another unique advantage of SoCs is their ability to debug FPGA designs. For debugging FPGA designs, information can be extracted from the FPGA using the microcontroller subsystem via a high-speed interface for debugging.
(4) Engineering tool costs. In contrast to the notion that FPGA development tools are expensive, Microsemi offers the free LiberoSoCIDE for FPGA development, with payment only required when developing high-end devices.
Industrial drive systems
An industrial drive system consists of a motor controller and a communication device. The motor controller contains the logic and protection logic for driving the inverter, while the communication device enables the monitoring and control to initialize and modify the running time parameters.
Figure 1: Typical industrial drive system.
In a typical drive system (Figure 1), multiple controller devices may be used to implement the drive logic. One device may perform calculations related to the motor control algorithm, a second device may run communication-related tasks, and a third device may run safety-related tasks.
Multi-axis motor control
Traditionally, industrial motor control applications have used microcontrollers or DSPs to run the complex algorithms required for motor control. In most traditional industrial drives, FPGAs are used alongside microcontrollers or DSPs for data acquisition and fast-acting protection. Aside from data acquisition, PWM generation, and protection logic, FPGAs have not traditionally played a major role in implementing motor control algorithms.
The method of implementing motor control algorithms using microcontrollers or DSPs is not easily extended to multiple motors running at independent speeds (multi-axis motor control). Microsemi SmartFusion2 SoC FPGA can implement integrated and complete multi-axis motor drive control using a single device (Figure 2).
Figure 2: Microsemi SmartFusion2 SoC FPGA uses a single device to achieve complete multi-axis motor drive control.
The control aspect can be divided into two parts. One part is used to run the Field-Oriented Control (FOC) algorithm, speed control, current control, speed estimation, position estimation, and PWM generation; the other part includes speed profiling, load characteristics, process control, and protection (faults and alarms). Executing the FOC algorithm is time-critical and requires extremely high sampling rates (in the microsecond range), especially for high-speed motors with low stator inductance. This makes implementing the FOC algorithm in an FPGA superior. Process control, speed profiling, and other protections do not require rapid updates and can therefore be executed at lower sampling rates (in the millisecond range) and can be programmed within the built-in Cortex-M3 subsystem.
Transistor switching cycles play a crucial role in the drive. If the FOC loop execution time is much shorter than the switching cycle, the hardware module can be reused to calculate the voltage of a second motor. This means that the device can provide higher performance at the same cost.
Figure 3: Block diagram of field-oriented control (FOC) for permanent magnet synchronous motors
(1) Motor control IP module. Figure 3 shows the sensorless field orientation control algorithm. This section will discuss these modules, which are provided as IP cores.
●PI Controller. A Proportional-Integral (PI) controller is a feedback mechanism used to control system parameters. It has two adjustable gain parameters for controlling the controller's dynamic response—the proportional and integral gain constants. The proportional component of the PI controller is the product of the proportional gain constant and the error input, while the integral component is the product of the accumulated error and the integral gain constant. These two components are summed. The integral phase of the PI controller can cause instability in the system because the data value increases uncontrollably. This uncontrolled data rise is called integral saturation, and all PI controller implementations include an anti-saturation mechanism to ensure that the controller output is finite. Microsemi's PI controller IP module uses a hold-on-saturation algorithm for anti-saturation. This module also provides additional features to set the initial output value.
● Field-Oriented Control (FOC). FOC is an algorithm that provides optimal current to a motor by independently determining and controlling the torque and magnetizing current components. In a permanent magnet synchronous motor (PMSM), the rotor is already magnetized. Therefore, the current supplied to the motor is only used for torque. FOC is a computationally intensive algorithm, but Microsemi's motor control reference design has been built for optimal use of device resources. The FOC algorithm includes Clarke, Park, inverse Clarke, and inverse Park transforms.
● Angle Estimation. One input to the FOC is the rotor angle. Accurately determining the rotor angle is essential for ensuring low power consumption. Adding physical sensors to determine position and velocity increases system cost and reduces reliability. Sensorless algorithms help eliminate sensors, but increase computational complexity. Microsemi offers two angle calculation algorithm IP modules for sensorless control—one based on a Luenberger observer and the other based on direct back EMF calculation. The company also offers separate reference designs based on Hall sensors and encoders.
●PLL. PLLs are used for synchronization signals and are useful in many applications, such as inverter angle estimation and grid synchronization.
● Rate Limiter. A rate limiter module enables smooth changes in system variables or inputs. For example, in a motor control system, if the required speed of the motor changes suddenly, the system may become unstable. To avoid this, a rate limiter module is used to transition from an initial speed to the desired speed. The rate limiter module can be configured to control the rate of change.
● Space Vector Modulation. The space vector modulation module improves DC bus utilization and eliminates short pulses from transistor switching. Because the transistor turn-on/turn-off time is longer than the pulse duration, short pulses can lead to incorrect switching behavior.
● Three-phase PWM generation. At the end of all calculations, the three-phase motor voltages are obtained. These voltages are used to generate the switching signals for the transistors in the inverter. The PWM module generates switching signals for six transistors (three high-side and three low-side) and features advanced characteristics such as dead time and delay time insertion. The programmable dead time insertion helps avoid catastrophic short circuits on the inverter pins. The programmable delay time insertion allows ADC measurements to be synchronized with PWM signal generation. This module can be configured to work with inverters consisting only of N-MOSFETs or inverters that include both N-MOSFETs and P-MOSFETs.
(2) Debugging FPGA Designs in a SoC. Generally, debugging a design on a microcontroller is simpler than debugging it on an FPGA. In a SoC, the high performance of the FPGA can be leveraged while maintaining the faster debugging advantage of the microcontroller. The microcontroller subsystem and FPGA architecture in Microsemi's SmartFusion2 SoC FPGA can communicate with each other via the AMBAAPB or AXI bus. This allows test data to be injected into or recorded from the FPGA architecture, facilitating internal data visualization during runtime for real-time debugging. Firmware code can be step-by-step, and breakpoints can be set within the code to analyze FPGA register data.
The multi-axis motor control solution based on SmartFusion2SoCFPGA connects to a host PC via USB and communicates with a graphical user interface (GUI) to start/stop the motor, set motor speed values and other system parameters, and describe up to four system variables, such as motor speed, motor current and rotor angle (Figure 4).
Figure 4: Screenshot of the GUI - drawing internal parameters: rotor angle (green), Valpha (red), Vbeta (black), motor speed (blue).
(3) Ecosystem. Microsemi offers a rich library of IPs, including several motor control functions discussed earlier. These modules are easily customizable and portable to Microsemi devices. Using the SmartDesign tool in LiberoSoC software, these modules can be graphically configured and connected. With the help of these IP modules, designers can significantly reduce the time required to implement motor control algorithms in FPGAs.
These IP modules have been tested on motors operating at speeds up to 30,000 r/min and switching frequencies of 200 kHz.
Industrial communication protocols
The trend in industrial networking is to replace point-to-point communication with faster network communication. Achieving such high-speed communication requires supporting higher bandwidth, which is not easy for microcontrollers or DSPs that simultaneously handle motor control algorithms. In most cases, an additional microcontroller or FPGA is used to handle communication with each motor controller. Commonly used Ethernet-based protocols include PROFINET, EtherNet/IP, and EtherCAT standards, which are still evolving. Other protocols include CAN and Modbus. The advantage of using a SoC in this context is that it supports multiple industrial Ethernet protocol standards on a single FPGA platform.
Depending on the end system objectives, system cost can be optimized by reusing IP and protocol stacks (for communication), or performance can be optimized by carefully partitioning functions in hardware (FPGA) and software (ARM Cortex-M3 subsystem).
Microsemi's SmartFusion2 FPGA features built-in CAN, high-speed USB, and Gigabit Ethernet modules as part of its microcontroller subsystem. The high-speed SERDES module is used to implement protocols involving serial data transmission.
Security
SmartFusion2 SoCFPGA devices feature several design and data security features. Design security features such as DPA-certified anti-tamper protection and encryption features help protect customer intellectual property. SoCFPGA devices also include data security features such as ECC hardware accelerators, AES-128/256, and SHA-256 services. For data security, EnforcITIP Suite and CodeSEAL software security components can be used. EnforcITIP includes a set of customizable kernels (as a netlist), effectively moving the security layer into the hardware. CodeSEAL injects countermeasures into the firmware and can be used independently or as an enhancement to EnforcIT.
The flexibility in implementing the protocol allows designers to use multiple security layers to authenticate information entering from the central monitoring controller.
reliability
The growth of security standards in multiple markets has driven the demand for high reliability. SmartFusion2 is designed to meet the needs of high availability, safety-critical, and mission-critical systems. The following are some of the reliability features offered by the SmartFusion2 SoC FPGA.
(1) Single-event upset (SEU) immune zero-fIT rate configuration. High-reliability operation requires an SEU-immune zero-fIT rate FPGA configuration. The SmartFusion2 architecture is immune to alpha or neutron radiation because it uses flash memory to configure the routing matrix and transistors used in the logic modules. SRAM-based FPGAs may have a FIT (time failure) rate of 1k to 4k at sea level, and much higher at altitudes above 5,000 feet. High-reliability applications can tolerate FIT rates below 20, making SmartFusion2 ideally suited for these applications.
(2) EDAC protection. The SmartFusion2 device features an error detection and correction (EDAC) controller to prevent single-event upsets in the microcontroller subsystem (MSS) memory.
(3) No external configuration device. In complex systems with a large number of FPGAs, using an external configuration device can reduce reliability. FPGAs require time to configure upon power-up, which adds design complexity in applications using multiple FPGA devices. The SmartFusion2SoCFPGA includes configuration memory internally, providing the added advantage of being enabled as soon as the device powers on.
(4) Military-grade temperature devices. The SmartFusion2 SoC FPGA device has been fully tested for military-grade temperature conditions. The military-grade device features 10k and 150k logic cells and includes security features that allow access to the cryptographic accelerator and data security features.
Summarize
Microsemi's SmartFusion2 SoC FPGA offers several features that reduce the TCO of industrial designs, utilizing highly optimized motor control IP modules and proven reference designs. Customers migrating from microcontrollers will be able to reuse some legacy code, while FPGA designers will be able to leverage the FPGA architecture and ARM Cortex-M3 subsystem to create a high-efficiency architecture that allows motor control and communication modules to reside simultaneously in a single device. The presence of the ARM Cortex-M3 microcontroller subsystem enables flexible design and intelligent partitioning, optimized for performance and cost. The microcontroller subsystem can also inject and log data at runtime, accelerating FPGA design debugging. The SmartFusion2 platform also offers a wide range of options for implementing industrial communication protocols. It provides multiple security features for design and data security, as well as features that meet high reliability requirements. The SmartFusion2 family of devices is supported by a robust ecosystem that helps customers develop industrial solutions with minimal TCO.
