Abstract: Addressing the issues of high installation costs, blind spots, and excessive number of video capture terminals required by traditional fixed surveillance systems, this paper proposes a mobile video surveillance system based on an ARM and FPGA architecture, along with its hardware and software implementation. This system enables comprehensive real-time capture of user-required information while reducing the number of video capture nodes. The system comprises a motor control module, a video capture module, and a wireless network control module, realizing a wireless video surveillance system. Based on a Linux operating system, a web server, and a video encoder, it allows users to remotely view the target site via the Internet.
China's video surveillance market is developing rapidly, with digital surveillance gradually becoming mainstream. Networking, personalization, and intelligence will be important development trends in the Chinese video surveillance market. However, current streaming media transmission technologies have high network requirements, hindering widespread adoption, and fixed monitoring costs are too high. How to integrate video surveillance with the Internet, enabling monitoring personnel to conduct monitoring anytime, anywhere, is a pressing issue for modern surveillance technology. On the other hand, current video surveillance systems mostly use ARM9 and ARM11 series microcontrollers. ARM microcontroller hardware peripherals are fixed at the factory, making hardware expansion and upgrades difficult for users. Multi-chip solutions combining ARM and FPGA lead to excessively high system costs, wasted system resources, and excessive power consumption. To address these shortcomings, this paper proposes a new solution using a Zynq series processor. The chip combines a high-performance Cortex-A9 dual-core processor with an FPGA. The ARM portion handles high-definition video processing, while the programmable logic FPGA portion allows for hardware upgrades and expansion.
1. Mobile Video Surveillance System Architecture
The main control board of this design is the ZedBoard development board of Digilent, and the main chip Zynq7020 is integrated with a high-performance dual-core ARM Cortex-A9MPCore processing system and programmable logic [1]. The video acquisition end is located on the mobile car, so as to achieve the purpose of mobile video acquisition. The design of the system mainly includes the design of the ARM control part and the design of the FPGA logic part. The ARM part is mainly used to run the operating system and application software on the system, such as the Web server Boa and the video encoder mjpg-streamer; the FPGA part is mainly used to expand hardware resources and design the PWMIP core of the car motor drive part. The overall structure block diagram of the system is shown in Figure 1. The functions of each module are as follows: the camera is responsible for video image acquisition, the Zynq main control module is responsible for the ARM operating system part and the FPGA logic resource part, the motor control module is responsible for the movement of the smart car, the BoaWebserver is responsible for network interaction, and the wireless router is responsible for the transmission and reception of wireless network data.
After the system is powered on, the chip initialization program embedded in the chip is executed automatically first, and then the first-stage bootloader FSBL is executed. The bit stream file (bit file generated by the PWMIP core design) is used to configure the FPGA part. After the FPGA is configured, the U-boot boot program is executed to start the Linux operating system [2]. After the system is started, the smart car generates a wireless signal through the wireless router. The user can connect to the smart car terminal through the network on the other end to implement video monitoring. The interaction between the user and the system is shown in Figure 2.
This article mainly introduces the design of the motor control part, specifically including the design of the hardware circuit of the motor control part, the design of the PWMIP core of the FPGA part, and the design of the PWM driver of the Linux operating system.
2. Design of the motor control section
2.1 Design of the hardware circuit for the motor control section
This module is mainly implemented by the L298P dual H-bridge DC motor driver chip. Since one L298P chip can drive two DC motors, and the car has four wheels, two L298P chips are needed [3]. At the same time, in order to reduce the number of FPGA I/O pins used, the SN74HC02D quad two-input NOR gate chip is used in the schematic design, so that two I/O pins can control the four input terminals of L298P. DIR1, DIR2, PWM1, and PWM2 are connected to the FPGA through the PMOD interface of the Zedboard. The schematic diagram is shown in Figure 3. In the figure, IN1, IN2, IN3, and IN4 are input signals, and ENA and ENB are enable signals. ENA controls the input enable of IN1 and IN2, and ENB controls the input enable of IN3 and IN4. When ENA is 1 and DIR1 is 1 (that is, when IN1 is 0 and IN2 is 1), the motor on the P1 interface rotates forward; when ENA is 1 and DIR1 is 0 (that is, when IN1 is 1 and IN2 is 0), the motor on the P1 interface rotates in reverse; when ENA is 0, the motor on the P1 interface stops. The principle is the same for the motor connected to the P2 port.
2.2 Design of PWM IP Core in FPGA Section
The design of Xilinx's embedded system is implemented by its EDK (Embedded Development Kit) development kit. EDK has a complete set of tools to complete the embedded system design, namely: hardware design tool XPS (Xilinx Platform Studio) and software design tool SDK (Xilinx Software Development Kit). The hardware design steps are as follows: (1) Set the new project path;
(2) Customize IP configuration for peripherals;
(3) Create a UCF file;
(4) Generation of bit stream [4]. The custom IP part mainly implements the forward, reverse and stop control of the motor. The key VerilogHDL code is as follows:
case (state)
//Motor stopped
′NOP: {pwm_left, pwm_right}<={7′d0, 7′d0};
'GOING: //Motor rotates in the forward direction
begin
if (dis_value>31)
{pwm_left, pwm_right, dir_lself, dir_rself}
<={7′d100, 7′d100, 1′d0, 1′d0};
else
{pwm_left, pwm_right, dir_lself, dir_rself}<=
{{dis_value[4:0], 2′b0}, {dis_value[4:0], 2′b0}, 1′d1, 1′d1};
end
RETURN: // Motor rotates in reverse
begin
if (dir_value == 3'b010)
{pwm_left, pwm_right, dir_lself, dir_rself}<={7′d80, 7′d80, 1′d1, 1′d0};
else
{pwm_left, pwm_right, dir_lself, dir_rself}<={7′d80, 7′d80, 1′b0, 1′b1};
end
endcase
In this design, the amount of data transmitted for motor control is relatively small. Only a low-speed AXI4-Lite bus device PWM module needs to be added to control the PMOD interface to achieve communication between hardware devices. The global ACLK of AXI4-Lite is set to 100MHz, the starting physical address of the PWM module is 0x6CA00000, and the space size is 64KB. The PWM configuration information is shown in Figure 4.
2.3 Design of Motor Driver under Linux
Since remote transmission is implemented under the TCP/IP protocol in the Linux system, by writing the IP driver under Linux, the application can access the FPGA's PMOD interface device through the standard Linux interface. This design is a character device driver, which includes device loading, device unloading and file operation functions. When the PWM module is loaded, the system calls the module_init(pwm_init) macro to implement the module initialization operation. In this system, the pwm_init() function mainly completes the following tasks: (1) registering the character device driver in the kernel; (2) creating the PWM device class; (3) creating the device using the PWM device class; (4) mapping the physical address of the PWM module to the virtual address [5]. Some key code is shown below:
//Physical address allocated by XPS
#definePWM_MOUDLE_PHY_ADDR0x6CA00000
//Register driver
pwm_driver_major=register_chrdev(0, DEVICE_NAME, &pwm_driver_fops);
pwm_driver_class=class_create(THIS_MODULE,"
pwm_driver); // Create device class
pwm_driver_device=device_create(pwm_driver_class, NULL, MKDEV(pwm_driver_major, 0), NULL, "pwm_device");
// Create a device using the device class
//Map the PWMIP physical address to a virtual address
pwm_fre_addr=(unsignedlong)ioremap(PWM_MOUDLE_PHY_ADDR, sizeof(u32));
Initialization is complete, but the device still won't work with just the initialization function; a mechanism to adjust the frequency and duty cycle is also needed. The frequency control function for the PWM is shown below:
staTIcssize_tsys_pwm_frequency_set(structdevice*dev, structdevice_attribute*attr, constchar*buf, size_tcount)
{
longvalue = 0;
inti;
frequency=0;
//Disable the PWM module before modifying the frequency.
outl(value,pwm_fre_addr);
// Convert the string written to pwm_frequency to an integer.
for (i=0; i100000000) value=100000000;
value = 100000000 / frequency;
// Write the count value to the pwm_fre_addr register of the PWM module.
outl(value,pwm_fre_addr);
returncount;
}
The function that controls the PWM duty cycle is the same as the function that controls the PWM frequency.
3. Experimental Results and Tests
The system's main control board is a Zedboard development board. After power-on, the wireless router will publish a wireless network with the SSID Tp_Link_5C90, which can be connected to by any device with internet access. Entering the URL 192.168.1.100 in a browser will log you into the mobile video surveillance webpage, where you can control the video terminal using the buttons on the interface.
This design utilizes the Xilinx AllProgrammable Zynq chip as the main control CPU, with the FPGA section enabling logic expansion and functional supplementation. For example, it allows for custom communication protocols and IP cores. Furthermore, Xilinx's reconfigurable technology can be leveraged to upgrade the hardware system, facilitating future expansion and hardware upgrades. The ARM section employs a high-performance dual-core Cortex-A9, ensuring smooth processing of high-definition video and overall system stability. Compared to traditional analog monitoring, digital video processing technology significantly improves image quality and monitoring efficiency.
The design employs a hardware-software co-design approach, which involves simultaneously designing and coordinating the hardware and software based on the overall system definition. This includes the division of hardware and software (which functions are implemented in software and which in hardware), the development and joint debugging of the hardware and software systems, which reduces development risks and shortens the development cycle.
References
[1]XilinxInc.UG585，Zynq-7000AllProgrammableSoCTechnicalReferenceMannual[Z].2013.
[2] Xilinx Inc. UG873, Zynq-7000 All Programmable SoC: Concepts, Tools and Techniques [Z]. 2013: 12-35, 40-53.
[3] Wang Fangfang, Zhang Huan. Design of dynamic smart home system based on Zynq platform [J]. Software, 2013, 34(8): 98-100.
[4] Hu Dianrong, Guo Chunsheng. Design of SPI and Ethernet transmission based on ZedBoard [J]. Journal of Hangzhou Dianzi University, 2013, 33(5): 126-129.
[5] Lu Jiahua, Jiang Zhou, Ma Min. Embedded System Hardware and Software Co-design Guide: Based on Xilinx Zynq [M]. Beijing: China Machine Press, 2013.
