A programmable digital downconverter (DDC) based on FPGA was designed and implemented for use in a broadband digital intermediate frequency (IF) software radio receiver. Its main functions include digital downconversion and data extraction. A top-down modular design approach was adopted, dividing the entire downconverter into basic units, implementing these functional modules, and forming a module library. In practical applications, the configuration of each module was optimized to meet the performance requirements of the specific wireless communication system.
Digital downconversion technology has significant application value in mobile communications, digital broadcasting, television, and other fields. In the receiver, the signal is mixed and then output to a low-pass filter to filter out harmonic components and out-of-band signals. However, with the increase of sampling rate, an important problem is that the data stream rate after sampling is very high, which leads to the subsequent signal processing speed not keeping up, especially for some synchronous demodulation algorithms, whose computational load is huge [1]. Excessively high data throughput makes it difficult to meet real-time requirements, so it is necessary to reduce the speed of the data stream after A/D conversion.
The basic function of digital downconversion is to extract the required narrowband signal from the input broadband high-speed data stream signal, downconvert it into a digital baseband signal, and convert it into a lower data stream [2]. The output signal of the high-speed ADC is sent to the digital downconverter , then orthogonally mixed with the digital local oscillator, and then filtered by a bandpass filter to remove other interference signals before demodulation and decoding. If the mixed data is directly bandpass filtered, the computational load is particularly large. For example, if the digital sampling rate of the signal is 30.72MHz and the filter is a 33rd order FIR filter, the filtering operation requires 1013M multiplications and 980M additions, which is difficult for a conventional DSP to handle. Therefore, the mixed signal must be slowed down, which is the main work of the downconverter, as shown in Figure 1.
1. Principle and Implementation
1.1 System Principle Implementation
The subsequent processing of the output signal of the digital downconverter mainly involves signal demodulation, decoding, anti-interference, adaptive equalization, and signal parameter estimation [3]. Since the I/Q baseband signals after orthogonal decomposition usually bring great convenience and good performance to the above-mentioned subsequent processing, this design adopts a typical structure of orthogonal two-way processing. Figure 2 is the structural block diagram of this design. It mainly includes: digitally controlled oscillator, mixer, improved cascaded integrator comb (MCIC) filter, half-band (HB) filter, decimator, programmable FIR filter, and control module.
The analog intermediate frequency (IF) signal is sampled by the front-end analog-to-digital converter (ADC) to obtain the digital IF signal. This digital signal is first mixed with two quadrature local oscillator (LO) signals generated by a digitally controlled local oscillator (DCO), shifting the digital IF signal to the baseband. Since the ADC samples at the IF, the sampling rate can be very high, and the data rate obtained after mixing is consistent with the sampling rate. Directly using an FIR filter would not achieve this processing speed. Therefore, the mixed signal first passes through a CIC filter and an HB filter, then undergoes decimation to reduce the data rate, and is then filtered again by an FIR filter. Because all coefficients of the CIC filter are 1, its implementation is very simple, involving only addition and subtraction operations. Hardware implementation can achieve a high processing speed, making it suitable as the first stage in a decimation system for large decimation factors. However, the stopband attenuation characteristic of the CIC filter is not very good, typically requiring a five-stage cascaded CIC filter to increase stopband attenuation, with decimation factors ranging from 2 to 16. Since the in-band flatness of the CIC filter is not very good, a compensator is added at its end, and these are collectively referred to as an improved CIC (MCIC) filter. The HB filter, with almost half of its coefficients being zero, reduces the computational load by half during filtering, and is therefore used as a second-stage low-pass filter. The decimation factor of the signal processed by the HB filter is fixed at 2, making it particularly suitable for reducing the sampling rate by half. After decimation by the MCIC and HB filters, the baseband signal is reduced from its initial high data rate to a lower rate, making it suitable for subsequent FIR filter processing.
1.2 Implementation Principle of Numerical Control Oscillator
A numerically controlled oscillator (CNC) is a local frequency oscillation signal generator. Its main function is to generate an ideal sine and cosine sequence with an oscillation frequency at the intermediate frequency [4]. It is one of the most important factors determining the system performance. The CNC oscillator in this paper is implemented using direct digital frequency synthesis technology.
Direct Digital Frequency Synthesis (DDS) is a novel frequency synthesis technique that directly synthesizes the desired waveform based on the concept of phase. In recent years, continuous advancements in technology and devices have led to the rapid development of DDS, representing a leap forward in frequency synthesis technology and making it the most widely used frequency synthesis technique today. The basic structure of DDS is shown in Figure 3.
1.5 Implementation Principle of Programmable FIR Shaping Filter
In the multi-stage high-efficiency digital filter module of a digital downconverter, the last stage generally uses a programmable FIR filter to filter the entire channel. After the signal is decimated by the preceding MCIC filter and half-band filter, the sampling rate input to the FIR filter is relatively low. Therefore, under the premise of real-time processing, the order of the filter can be appropriately increased. Higher-order FIR filters can make the filter's passband ripple, transition bandwidth, stopband attenuation and other indicators better designed [7].
The design goal of this FIR filter is to allow the desired signal to pass through as much as possible while suppressing unwanted signals as much as possible. In terms of the filter's amplitude-frequency characteristics, this means minimizing passband ripple, ensuring the passband width is as close as possible to the bandwidth of the desired signal, minimizing the transition band, and maximizing stopband attenuation. The programmable FIR filter designed in this paper is implemented directly using an IP core, with an order of 64, and still employs a series-parallel combined structure.
2. System Verification
The FPGA chip selected for this design is the Virtex II 3000 from Xilinx. The chip resource utilization is shown in Table 1.
The input signal is selected as x = cos(2π(fc + f1)t + 0.0032cos2π(fc + f0)t), where f1 = 0.3MHz, f0 = 0.2MHz, fc = 30MHz. The selected sampling frequency is fs = 80MHz, and the decimation coefficients are CW1 = 4, CW2 = 4, and CW3 = 1. That is, the first-stage CIC filter performs a decimation of 5 times, the second-stage CIC filter performs a decimation of 5 times, and the entire system performs a decimation of 100 times. The amplitude spectrum of the dual-output complex signal is shown in Figure 6. The spectrum shows that the dynamic range of the digital down-converter is greater than 50dB.
This paper primarily studies the design of a digital down-converter based on FPGA. First, the overall design scheme of the digital down-converter is demonstrated based on objective requirements and the total available resources. Then, the entire design is modularized according to the design scheme, adopting a top-down modular design approach to complete the design of each module. By configuring each decimation pin, a decimation factor of 8 to 1024 times can be achieved. Finally, using a sine wave signal as the test signal, the maximum dynamic range of the system is measured to be greater than 50 dB.
