To address the data communication requirements between the 8-core DSP TMS320C6678 and external devices, a hardware circuit for a Gigabit Ethernet communication interface was designed, using the on-chip integrated Gigabit Ethernet switching subsystem as the core and selecting the 88E1111 chip as the PHY device. The Ethernet low-level driver and TCP/IP protocol programming were completed on the embedded operating system SYS/BIOS and the network development environment NDK. Ethernet communication tests between the DSP and a host computer demonstrated the correctness and practicality of the Ethernet interface circuit hardware and software.
With the increasing application of DSP processors in modern industry, their functions extend beyond fast computation and processing. They also need to exchange data in real time with other processors or devices to achieve resource sharing. Therefore, selecting a stable, fast, and efficient interface method to meet the needs of different devices is a crucial component in the design of modern digital signal processing systems.
TI's 8-core processor TMS320C6678 (hereinafter referred to as C6678) provides abundant on-chip interface resources for communication between the processor and peripherals. These interfaces can all be used for communication between the DSP and peripherals, but their flexibility varies. Using the SGMII interface to implement Gigabit Ethernet communication can generalize the communication interface and make it suitable for a wide range of device connections.
This paper focuses on the characteristics of the C6678 chip and its interface resources, and designs and implements gigabit Ethernet communication. The main designs include Ethernet interface circuit, network underlying hardware driver, and TCP/IP protocol user program. The Ethernet communication test with the host computer was completed, realizing high-speed and efficient network transmission of digital signals.
1C6678 Ethernet Switching Subsystem
The C6678 is an 8-core high-performance fixed-point/floating-point processor based on the KeyStone I architecture, with a maximum single-core operating frequency of 1.25 GHz. The C6678's Ethernet switching subsystem includes two Ethernet Media Access Controllers (EMACs), two SGMIIs, one Management Data Input/Output (MDIO), a 3-Port Ethernet switching module, and a network configuration bus, as shown in Figure 1.
Figure 2 Internal Structure
The role of EMAC is to convert the internal signals of the switching subsystem into GMII signals and pass them to the SGMII module; MDIO controls the physical layer chip to perform control input and output for multiple data streams.
2PHY chip 88E1111
This paper selects the C6678 as the main chip. Since the C6678's gigabit network switching subsystem only supports the SGMII interface, this paper selects the 88E1111 physical chip, which has good compatibility with network data transmission of the SGMII interface. The internal structure of the 88E1111 chip is shown in Figure 2.
The 88E1111 has two media interfaces: a copper media interface and a fiber optic interface. The copper media interface is MDI[3:0], and the operating mode is selected by setting HWCFG_MODE[3:0]. The MDIO module integrated into the 88E1111 connects to the MDIO interface of the EMAC, which allows the network control terminal to easily read the physical chip status register, achieving real-time monitoring.
3 Hardware Interface Design
This paper designs the interface between the C6678 on-chip Ethernet switching subsystem and the external PHY chip 88E1111 and its peripheral circuits. The main components include: the connection between the C6678 and the 88E1111 chip, the configuration of the 88E1111 chip, and the connection between the 88E1111 chip and the network medium.
3.1C6678 and 88E1111 chip connection
The interface circuit between the C6678 and the PHY chip 88E1111 is shown in Figure 3. The 88E1111 operates in SGMII interface mode, which does not require a TXCLK clock input, thus helping to reduce the number of traces on the circuit board and also reducing noise generation.
The main interface signals, including clock and data signals, are as follows:
MDIO_CLK: Management data clock. This clock signal is provided by the on-chip MDIO module of the C6678, and its frequency is controlled by configuring the CLKDIV bit in the MDIO control register CONTROL.
SGMII_TXP and SGMII_TXN: Serial transmit differential data lines. They connect the DSP's internal SerDes pin to the S_IN pin of the physical chip. The DSP's SerDes pin transmits serial data to the physical layer through these pins, and the data includes the transmit clock signal.
SGMII_RXP and SGMII_RXN: Serial receive differential data lines. They connect the DSP's internal SerDes pin to the S_OUT pin of the physical layer chip. The physical layer chip transmits data to the DSP's SerDes through this interface, and the data includes the data receive clock signal.
MDIO: Management Data I/O. It can connect up to 32 PHY devices to the DSP's EMAC and enumerate all PHY devices, reading their status registers to monitor connection status. The data frame structure conforms to the 802.3 standard and includes read/write instructions, PHY address, register address, and data.
Because the MDIO integrated on the 88E1111 uses a different voltage when connected to the MDIO module integrated on the C6678 (2.5V for the former and 1.8V for the latter), a voltage converter should be added between them. This article uses a PCA9306 to implement the level conversion between 2.5V and 1.8V, and its connection circuit is shown in Figure 4.
3.288E1111 chip configuration
The 88E1111 connects to the MDIO module of the C6678. MDIO can recognize up to 32 physical chips. Before using a physical chip, it needs to be configured. The configuration mainly includes the chip's address, mode, etc. The configuration of the CONFTG[6:0] pin definitions can be found in the literature. The hardware circuit configured in this paper is shown in Figure 5. In Figure 5, a resistor can be omitted. For the convenience of testing, a 0Ω resistor is added in this paper.
After the 88E1111 hardware configuration is completed, the system will be fixed to one interface mode. According to the definition in the literature, the physical chip address is: PHY_ADDRESS=0'b00001, and the chip mode is: SGMII mode without clock and auto-negotiation.
3.388E1111 chip connected to RJ45
The 88E1111 and network media cannot be directly connected. Due to the gigabit transmission speed, a suitable network isolation transformer is needed to reduce transmission loss, echo, and crosstalk. This paper selects the HR911130C gigabit Ethernet socket, which has a built-in transformer circuit. Stable network signal transmission can be achieved simply by connecting an external filtering network. The 88E1111 and HR9111130C use a differential connection, requiring strict length matching during PCB routing. Impedance matching networks are also generally required, as shown by R1 and C1 in Figure 6.
4 Software Programming
TI has released the Network Development Kit (NDK) for network development. The NDK network framework handles the configuration of multiple modules, and data packet splitting and parsing are also handled by the developers, accelerating the network development process. The NDK is built on top of the real-time operating system SYS/BIOS. It interacts with the BIOS through the OS abstraction layer, and the BIOS's cfg configuration file provides a visual overview of the various NDK modules.
