The CPU self-test phase includes CPU self-diagnostic tests and a reset watchdog timer.
During the self-diagnostic testing phase, the CPU monitors the status of each PLC module. If any abnormality is detected, it immediately diagnoses and addresses the issue, simultaneously issuing a fault signal and illuminating the LED indicator on the CPU panel. In the event of a fatal error, the CPU is forced into STOP mode, halting program execution. This CPU self-diagnostic testing helps to promptly detect or predict system faults, improving system reliability.
A watchdog timer (WDT) is a hardware clock within the CPU used to monitor the scan time of the PLC . The CPU sets a predetermined scan time before operation, and monitors the scan time in each scan cycle to ensure it doesn't exceed the specified value. This prevents system failure due to the PLC entering an infinite loop or executing unintended programs. If the program runs normally, the WDT is reset (cleared) during the internal processing phase of each scan cycle. If the program malfunctions and enters an infinite loop, the WDT will not be cleared in time, triggering a timeout overflow, and the CPU will issue an alarm signal or stop operating. Using WDT technology is also an effective measure to improve system reliability.
2 Communication Processing Stage
During the communication processing phase, the CPU checks for communication tasks. If a task exists, it calls the corresponding process to complete the communication processing with other devices (e.g., intelligent modules with microprocessors, remote I/O interfaces, programmers, HMI devices, etc.) and processes the communication data accordingly.
3. Read Input
During the input reading phase, the PLC scans all input terminals and stores the on/off state of each input terminal in the corresponding input image register, refreshing the value of the input image register. Afterward, the input image register is isolated from the outside world; its contents remain unchanged regardless of changes in peripheral input conditions. Changes in the input terminal state are only picked up during the input reading phase of the next scan cycle. This ensures that the same input signal state is used within a single scan cycle. Therefore, it is important to ensure that the width of the input signal is greater than one scan cycle; otherwise, signal loss is highly likely.
4. Execution phase
The user program of a programmable logic controller (PLC) consists of several instructions, which are arranged sequentially in memory. When the PLC is in run mode and executing the program, the CPU scans the user program sequentially. If the program is represented by a ladder diagram, the instructions are executed one by one, from top to bottom and from left to right. For each instruction scanned, the required input signal status is read from the input image register, rather than directly using the on/off state of the field input terminals. During the execution of the user program, corresponding calculations or processing are performed according to the instructions. The result of each calculation is not directly sent to the output terminal to immediately drive the external load; instead, the result is first written to the output image register. The value in the output image register can be used by subsequent read instructions.
5. Refresh Output Phase
After executing the user program, the output refresh phase begins. The programmable controller sends the on/off state from the output image register to the output latch, driving the user output device or load through the output terminals to achieve the control function. The value of the output latch is retained until the next output refresh.
After the refresh output phase ends, the CPU enters the next cyclic scan cycle.
