Abstract: Synchronous buck regulators are commonly used power supplies. With increasingly demanding application requirements, the industry is increasingly pursuing designs with high energy efficiency, high reliability, and high power density. For example, point-of-load (PoL) power supplies used in wireless LANs are experiencing increasingly wider input voltage ranges, higher operating frequencies, and higher power densities. With technological advancements, it's even possible to integrate the entire power system into a single package. While the circuit structure of a synchronous buck regulator is inherently very simple, engineers still face considerable technical challenges in designing efficient and reliable synchronous buck regulators. This requires a deep and thorough understanding of the various operating states of the regulator circuit, as well as significant computational work. This article introduces techniques for rapidly designing efficient and reliable synchronous buck regulators, and utilizes ON Semiconductor's PowerSupply WebDesigner online design tool to help engineers overcome these technical challenges.
1. Dynamic performance design
To design a reliable synchronous buck regulator, its dynamic performance specifications, such as load response capability, must first be met. The selection of the output inductor and capacitor directly affects the regulator's dynamic performance, so the power circuit design of a synchronous buck regulator usually begins with the selection of the output inductor and capacitor.
1.1 Selecting an inductor
From a circuit design perspective, to achieve a fast transient response, the smallest possible output filter inductor and the smallest possible output capacitor must be selected. However, a small inductance value increases inductor current ripple, leading to an increase in the effective current in the inductor and thus increasing conduction losses. At the same time, the resulting increase in peak current will also significantly increase the switching losses of the control transistor.
Using a large inductor can reduce the current ripple in the inductor, thereby reducing the steady-state output voltage ripple. The resulting low peak current also helps to reduce the switching losses of the MOSFET. However, too large an inductor will not only lead to a relatively large DC impedance and high inductance loss, but also reduce the load response capability of the regulator, thereby reducing the dynamic performance of the regulator.
To select an appropriate inductor, it is generally assumed that the current ripple ΔILO is 30% of the average inductor current, and then the appropriate inductor value can be calculated directly using the formula below.
tDEAD(ON) is the total dead time between detecting Q1 gate turn-off and Q2VGs reaching the threshold.
tDEAD(OFF) is the time when the total dead zone between the gate turn-off of Q2 and the turn-on of Q1 is detected.
tDEAD(ON) is the internally adjusted or programmable delay time (adaptive dead time) of the driver between detecting that the gate of Q1 is turned off and that Q2 has started to turn on.
tDEAD(OFF) is the driver delay between detecting Q2 gate turn-off and Q1 turn-on. It is typically much longer than tDEAD(ON) to avoid false triggering of Q2.
PRgate is the loss distributed within the gate impedance of Q2.
PGDRV is the energy stored in the gate capacitance.
RDRV(SRC) is the internal impedance driven by Q2 when Q2 is turned on (source current).
RDRV(SNK) is the internal impedance of the Q2 driver when Q2 is turned off (draining current).
gFS is the forward transconductance of a MOSFET.
VSPEC is the gate voltage when the MOSFET impedance is RDS(ON).
CISS is the input capacitance when VDS is close to 0V, and is approximately 1.25 times the typical value of CISS in the datasheet.
The output capacitance and reverse recovery loss are related to the Coss and Qrr of the synchronous transistor Q2, and are mainly dissipated by the control transistor Q1. As shown in Figure 4.
Figure 4 shows the loss comparison for Q2.
The conduction loss PCOND of Q2 increases with increasing VIN, while the switching loss PSW increases only slightly with increasing VIN. However, the parasitic diode conduction loss PDcond and gate drive loss PRgate of Q2 are independent of VIN. Therefore, Q2 experiences its maximum loss when VIN is at its maximum.
In summary, the total loss of Q1+Q2 is maximized when VIN is at its maximum or minimum. Therefore, the interaction between Q1 and Q2 must be considered during the calculation.
3 Design Examples
The following design example demonstrates how to optimize the selection of control transistor Q1 and synchronous transistor Q2. If designing a 5V, 10A synchronous buck regulator with an input voltage VIN = 8-16V and an operating frequency FSW = 350kHz, considering a 20% safety margin and voltage oscillation at the switching node, a MOSFET with a rated voltage of 30V or higher and a rated current IDCONT ≥ 10.3A can be initially selected. Then, the MOSFET package requirements are determined based on specific application requirements. For simplicity, we choose a device in a 5x6mm PQFN (Power56) package. Considering the above selection criteria, ON Semiconductor's product lineup offers over 150 devices; we need to further select suitable Q1 and Q2 from these. Again, for simplicity, we will list 12 devices each for Q1 and Q2.
Figure 5. Loss comparison for Q2
For Q2, the loss is greatest when VIN = VINMAX. Among the 12 devices shown in Figure 5, the FDMS7656AS has the lowest maximum loss. However, since the parasitic parameters of Q2 affect the switching losses of Q1, the minimum Q2 loss does not usually mean the best overall energy efficiency. The total power consumption of Q1 and Q2 must be compared to find the optimal Q2 to achieve the highest energy efficiency.
Figure 6. Loss Comparison of Q1
For Q1, the loss is greatest when VIN = VINMAX or VINMIN. Among the 12 devices shown in Figure 6, FDMS8027S and FDMS8023S have the lowest maximum loss Q1 when VIN = VINMAX and VINMIN, respectively.
To optimize converter efficiency, Q1 with the lowest loss is first selected based on VIN, and then Q2 with the lowest output loss is selected. In this example, the optimal Q2 is the same regardless of whether VIN is minimum or maximum, which is FDMS7658AS (but this is not always the case, especially with a wide VIN range or high FSW), as shown in Figure 7.
Figure 7 Optimization of combinations Q1 and Q2
Since the total loss of Q1+Q2 is maximized when VIN=VINMAX or VINMIN, we need to compare the total losses and select the optimal combination with the lowest maximum loss. As shown in Figure 8, when FDMS8027S is selected as Q1 and FDMS7658AS as Q2, the maximum loss of Q1+Q2 is minimized.
Figure 8 Comparison of total losses in Q1 and Q2
PowerSupplyWebDesigner: A tool for quickly designing efficient and reliable synchronous buck regulators
The design examples above demonstrate that selecting the optimal Q1 and Q2 in the design of synchronous buck regulators requires a large amount of tedious and complex calculations. To help engineers quickly complete efficient and reliable designs, ON Semiconductor provides the powerful online design platform PowerSupplyWebDesigner to accelerate FET optimization, as shown in Figure 9.
Figure 9 PowerSupply WebDesigner online design platform
Using PowerTrainLoss, the SynchronousBuck power loop loss analysis tool in PowerSupplyWebDesigner, engineers can easily compare the data and performance of qualified MOSFET devices, automatically eliminate devices exceeding TJ limits, select design margins and operating temperature ranges, choose single or dual-package MOSFETs, filter devices based on rated voltage, current, or package, add parallel devices and gate damping resistors, and immediately calculate the losses for different Q1+Q2 combinations. After selecting Q1 and Q2, engineers can obtain various loss and efficiency curves for the power loop within the input voltage and load ranges, and perform complete analysis and comparison for different designs based on these curves and power loop efficiency summary tables. Finally, PowerSupplyWebDesigner provides circuit schematics in PNG format, component lists in Excel format, and complete PDF design reports, which engineers can save online for future reference or modification.
4. Summary
To meet industry trends towards high energy efficiency, high reliability, and high power density, the design of synchronous buck regulators requires comprehensive consideration of dynamic performance and energy efficiency. While optimized dynamic performance can be achieved relatively easily through careful adjustment of component values, techniques for managing and optimizing MOSFET power consumption are typically complex and cumbersome. ON Semiconductor's PowerSupplyWebDesigner can help simplify the design process and accelerate MOSFET optimization selection.
