Abstract: A set of PLC backplane bus protocol interface chips based on CPLD was designed. The protocol chips can distinguish between periodic and non-periodic data on the PLC backplane bus. The process of designing the state machine, protocol frame controller, and FIFO controller using Verilog HDL is described in detail. The experimental results of stable backplane bus operation at 25MHz verify the feasibility of the protocol chip design.
The Programmable Logic Controller ( PLC ) main unit supports the connection of expansion modules via a backplane bus. The backplane bus is a high-speed data path between the PLC main unit and I/O expansion modules, supporting I/O data refresh between the main unit and expansion modules. The technical level of the backplane bus determines the I/O expansion capability of the PLC product and is a core technology in PLC design and manufacturing. Currently, most PLCs use serial communication technology to implement the backplane bus. Serial buses have fewer leads, lower hardware costs, and are less susceptible to interference compared to parallel buses. Serial buses can improve the reliability of automated equipment in harsh factory and industrial environments. Optional serial communication technologies include I2C, UART, SPI, USB, and Ethernet. Generally, many microcontrollers used as PLC main chips integrate these peripherals. However, the communication speeds of I2C, UART, and SPI peripherals integrated within the microcontroller are too slow to meet the communication speed requirements of the backplane bus. Although USB and Ethernet offer fast communication speeds, they are universal interfaces, requiring microcontroller intervention during communication protocol processing. Since microcontrollers process data slowly, the overall communication speed remains slow. A large PLC typically acquires thousands of I/O data points in less than 1ms. To meet such high-speed communication requirements, a dedicated backplane bus must be designed.
1. Backplane bus working principle
As shown in Figure 1, the data communication process based on the backplane bus is as follows:
(1) The PLC host sends the command to the backplane bus through the host protocol chip; (2) The slave protocol chip sends the received command to the microcontroller of the expansion module. The microcontroller of one of the expansion modules responds and sends the response data to the backplane bus through the slave protocol chip; (3) The host protocol chip receives the response data and sends it to the microcontroller of the PLC host.
Figure 1 Backplane bus communication block diagram
The data sent from the PLC host to the backplane bus can be divided into two categories: one is I/O refresh data, which is periodic and the data exchange is very frequent; the other is diagnostic data, which is non-periodic and occurs less frequently.
2 Protocol Chip Design
This design defines the backplane bus as adopting a specification similar to SPI serial communication, with a total of 4 leads for communication, including clock signal SCLK, chip select signal SSEL, write data lead MISO, and read data lead MOSI; it supports simultaneous data transmission and reception by the master and slave, and the data bit format is shown in Figure 2. Data frames are transmitted when the SSEL signal is low.
Figure 2 Backplane bus data specifications
The signals include data/address signals, reset signal Reset, and interrupt signal INT.
The internal structure block diagrams of the master and slave protocol chips are the same, as shown in Figure 3.
The protocol chip internally includes a state machine controller, a frame controller, shift registers, a receive/transmit FIFO, and read/write buffers. Periodic and non-periodic data frames sent by the microcontroller are first written to the write buffer, then queued in the transmit FIFO for transmission. Driven by the SPI clock SCLK, the data frames are converted into serial data and sent to the backplane bus. Under the influence of the SPI clock, serial data from the backplane bus is received. Coordinated by the state machine and frame controller, valid data frames are extracted from the receive FIFO and placed into the read buffer, awaiting read by the microcontroller. If the data is non-periodic, an interrupt signal is sent to notify the microcontroller to retrieve it. Periodic data in the read buffer can be overwritten; newly received periodic data directly overwrites older periodic data. Non-periodic data is stored separately, cannot be overwritten, and is read and cleared by the microcontroller.
Figure 3 Internal structure block diagram of the protocol chip
The protocol chip allows the external microcontroller to access the read and write buffers when idle, eliminating the need for the microcontroller to frequently process periodic data via interrupt technology. It also allows the PLC master to access the slave's periodic data without waiting.
3. Protocol chip implementation based on CPLD
3.1 CPLD Chip Selection
This design uses the MachXO series chips from Lattice. This series of CPLDs integrates some FPGA functions. In addition to rich built-in LUT resources, it also has a large number of distributed SRAM bits and embedded SRAM blocks dedicated to FIFO design. It also has an analog phase-locked loop (PLL) to support clock signal multiplication, division, etc., and the I/O pins can be configured to be compatible with 1.2/1.5/1.8/3.3V levels.
3.2 Hardware Programming Based on Verilog HDL
This design uses Verilog HDL, a hardware description language, for programming the protocol chip. Verilog HDL allows for hierarchical description and timing modeling when designing digital chips. This design employs a hybrid design pattern, and the main modules include a state machine, protocol frame detection, and a FIFO controller.
1) State machine design .
The top-level module of the protocol chip is the state controller section. The protocol chip has four states, each handled by a state machine described in Verilog HDL. The pseudocode is as follows:
2) Protocol frame detection.
The frame checksum of this protocol chip is performed using a simple summation method. On the receiving side, if the sum of the useful data in the data frame matches the subsequent checksum bytes, the protocol is correct; otherwise, the frame is discarded. The code for calculating the protocol frame checksum is as follows:
3) FIFO design.
FIFO utilizes the embedded SRAM block resources of the MachXO series CPLD. Lattice's ispLEVER 7.0 software provides a configurable IP soft core, which can be implemented based on embedded SRAM blocks or using lookup tables. The IP core block diagram of FIFO is shown in Figure 4. The configurable parameters of FIFO include FIFO byte depth, EmptyFull, Almostempty and AlmostFull trigger byte depth, data width, and endianness.
Figure 4 Block diagram of the configurable FIFO controller IP soft core
3.3 Protocol Chip Integration
The Verilog HDL program was compiled and synthesized using Lattice's CPLD development software ispLEVER 7.0. After several attempts, the MachXO2280 chip from Lattice's MachXO series CPLDs was ultimately selected. The synthesized master protocol chip occupied approximately 60% of the CPLD resources, while the slave protocol chip occupied approximately 45%. The FIFO controller fully utilized the embedded RAM blocks within the MachXO2280 chip and employed a phase-locked loop to achieve high-frequency clock operation. Finally, the protocol chip functionality was verified and tested by downloading the program to the CPLD chip via the JTAG port using LSCispVM(R)System programming software.
4 Conclusion
The backplane bus protocol chip designed in this paper operates stably and passes the burst pulse test when the backplane serial bus clock frequency is 25MHz, the signal level is LVTTL, the baseboard lead length is 40cm, and one host is connected to three expansion modules, verifying the success of this protocol chip design. Since this protocol chip is specifically designed for the periodic and non-periodic data transmission of PLCs, the hardware-implemented protocol frame controller supports high-speed communication and data frame verification functions, avoiding data transmission errors, greatly reducing the software overhead of peripheral microcontrollers, and enhancing reliability. It is a set of protocol chips very suitable for PLC backplane buses or backplane bus systems requiring multi-module collaborative operation.
