In the metallurgical industry, the transmission of most control information relies on buses. Buses also enable real-time monitoring of various production and processing stages, making bus technology ubiquitous. Among these, VME computers are widely used due to their support for multiple CPUs, 64-bit addressing and data transmission capabilities, compliance with the IEC 297 standard, reliable and stable mechanical performance, reliable connectors, hot-swappable ports, and multi-vendor support. This section presents a practical example of using dual-port RAM to implement communication between a frequency converter and a VME.
1. Overall Structure
As shown in the figure, the entire communication consists of three parts: DSP, VME dual-port RAM.
1.1 DSP Section
This part is the core of the entire motor control system. The DSP is mainly used to generate PWM pulses to control the motor. The chip used in this project is the Texas Instruments TMS320LF2407A chip, which has two event managers and can generate up to 12 pulse signals. It integrates high-performance 10-bit ADC, SCI, SPI, CAN and other modules, truly realizing single-chip control with stable performance and powerful functions.
1.2VME bus
The VME bus, a 32-bit industrial open standard bus introduced by Motorola in 1981, is mainly used in industrial control environments to achieve high-speed data acquisition and real-time communication between devices on the bus. VME bus boards generally come in two sizes: a 3U height board with one bus interface J1, and a 6U height board with two bus interfaces, J1 and J2. Typically, each VME bus board has 96 pins for interfaces J1 and J2, arranged in three rows (A, B, C), with 32 pins per row. J1 is generally used for direct connection to the VME bus, the middle column of J2 is used to extend the address or data bus, and the other two columns can be user-defined for I/O, disk drives, and other peripherals. 1.3 Dual-Port RAM Dual-port RAM has two completely independent sets of data lines, address lines, and read/write control lines, allowing two CPUs to simultaneously access the same cell in the dual-port memory; it has two completely independent interrupt logics to implement handshake control signals between the two CPUs; it has two independent "busy" logics to ensure the correctness of simultaneous read/write operations on the same cell by two CPUs; it has strong compatibility, with read/write timing exactly the same as ordinary single-port memory, and access speed fully meeting the requirements of various CPUs. These features make dual-port RAM suitable for some applications requiring high speed and real-time communication. Dual-port RAM has two independent storage circuits, which are interconnected through a control arbitration circuit. Taking the IDT7024 as an example, this chip is a 4K*16 static memory with a typical power consumption of 750mW and a maximum access time of 15/17/20/25/35/55ns. It can use three methods—interrupt, busy logic, and semaphore—to coordinate the information exchange between the two sides.
2 Hardware Components
2.1 DSP Section
Using the TMS320LF2407A chip, to connect to the dual-port RAM, the DSP's 16-bit data lines and 12-bit address lines should be brought out, along with control signal lines: DS, R/W. 2.2 VME Bus: Here, a standard 6U chassis from VMIC is used, containing two bus interfaces, J1 and J2. Only J1 is used for communication. 2.3 Dual-Port RAM: The dual-port RAM has two sets of independent address and data lines. These are connected to the address and data lines of the DSP and VME buses respectively. The control signal lines of J1 and the DSP are connected to the GAL for logic control of the dual-port RAM, as shown in the diagram below. 3 Communication Flow: Here, we treat the VME as the master device and the DSP as the slave device. The DSP's read and write operations are controlled by the VME. It is important to note that the same address cannot be written to simultaneously or read while writing to prevent data errors during write and read operations. The following are the flowcharts for read and write communication:
If the VME "reads" data from the dual-port RAM, it first needs to determine whether the area to be read is being "written" by the DSP. This can be done by using a "signal flag". If the DSP is not operating on the area, the VME can read data from that area.
