1. Overall Structure of Embedded Soft PLC
Embedded soft PLCs share a CPU with the embedded system, eliminating redundant wiring between them, thus increasing system reliability and facilitating the implementation of many advanced functions. Information from the PLC can also be displayed on the embedded system's screen, and the PLC can be easily edited using the embedded system's editing keys.
1.1 Hardware Structure of Embedded Soft PLC
External input switches are connected to the FPGA's I/O ports after opto-isolation. The FPGA then decodes the input, and the FPGA connects to the CPU via the data address bus. This allows the CPU to obtain and set the operating status of the input via the data address bus. The hardware block diagram is shown in Figure 1.
1.2 Software Structure of Embedded Soft PLC
Embedded software PLC programs fall into two categories: one is the editing state, which implements the input and compilation functions of the PLC program; the other is the application program oriented towards the production process. The system software structure consists of four parts: the editing module, the compilation module, the execution module, and the monitoring module. The data flow between the modules of the software PLC system is shown in Figure 2.
2. Design and Implementation of Key System Components
2.1 Ladder Diagram Editor
Qt/Embedded is a version of Qt for embedded systems developed by Trolltech, the renowned developer of the Qt library. Qt/Embedded offers advantages such as high portability and cross-platform support. This system uses Qt to write the interface; the ladder diagram editor interface is shown in Figure 3.
2.1.1 Ladder Diagram Data Structure Design
Ladder diagram editors are convenient and logically intuitive. They utilize the internal data structure of ladder diagrams to achieve functions such as display, insertion, deletion, and code conversion.
In PLC language, various elements, including individual nodes (such as normally open contacts, normally closed contacts, etc.) and logic blocks (such as AND logic blocks, OR logic blocks), all contain the same operations, such as insertion, deletion, and drawing. The logic blocks that make up a ladder can be viewed as the parts that make up the ladder, and the sub-logic blocks and individual nodes that make up a logic block can be viewed as the parts that make up the logic block, conforming to a "part-whole" hierarchical structure. Object-oriented design principles can be adopted, using the composite pattern to recursively create a tree structure. Using the composite structure, the same operations can be applied to both composite and individual objects. In most cases, the difference between object composites and individual objects can be ignored, simplifying program code and enhancing software maintainability. A class diagram using the composite pattern is shown in Figure 4.
In the diagram: `LadderElement` is an abstract class that serves as an interface for composite objects. It represents any graphical element in the ladder diagram language, which can represent both components and logic blocks. Where appropriate, it can implement the default behaviors common to all classes, such as drawing and code conversion. `LadderCell` is the base class for all component classes (such as normally open contacts, normally closed contacts, outputs, setters, and resetters). `LadderBlock` is the base class for all logic blocks (such as AND logic block classes and OR logic block classes).
Figure 5 shows a ladder and its corresponding data structure. OrBlock is an object of the OR logic block class, AndBloek is an object of the AND logic block class, and Rung is an object of the ladder class.
In addition, to facilitate drawing and editing, an empty component class is introduced. Its function is to represent the horizontal connecting lines in the ladder diagram. This is achieved by inheriting from the LadderCell class and reimplementing the member function Draw() to draw a horizontal line segment.
2.1.2 Design and Implementation of Editing Functions
Define a structure:
The screen is divided into a certain number of small regions, and two-dimensional arrays containing the same number of regions are created. When drawing a component, the component, the logic block it belongs to, and the ladder pointer it belongs to are saved in the array. The index of the two-dimensional array can be obtained by the coordinates of the cursor on the screen, thus allowing the corresponding objects in memory for the component, logic block, and ladder at the cursor's location.
Editing a ladder diagram is achieved by modifying its data structure in memory; after the data structure is changed, the diagram is redrawn. Editing a ladder diagram includes inserting components, inserting branches, inserting rungs, deleting components, and deleting rungs. Due to space limitations, only a brief introduction will be provided.
Component Deletion: After deleting a component LadderCell(A) from a LadderBlock, if only one LadderCell(B) remains in the LadderBlock, LadderCell(B) replaces the LadderBlock and is inserted into the parent LadderBlock; if only one LadderBlock(B) remains, all LadderElements of LadderBlock(B) are inserted into the parent LadderBlock. The ladder diagram and its data structure after deleting component X004 in Figure 5 become as shown in Figure 6.
Inserting a branch: Select the start and end positions of the branch twice on the screen using the cursor. These two positions must belong to the same AndBlock (A). After selecting the start and end positions, use the LadderElement between the two positions as a branch to form an AndBlock (B) and calculate the number of columns n occupied by AndBlock (B). Then, create a new AndBlock (C) to represent the inserted branch, and insert n empty elements into AndBlock (C). Create an OrBlock and insert AndBlock (B) and AndBlock (C) into OrBlock. OrBlock represents the OR logic block after the branch insertion. OrBlock replaces the positions of the elements between the two selections in their parent logic blocks. Then, draw the ladder diagram after the branch insertion based on the modified data structure. Figure 7 shows the changes in the ladder diagram before and after inserting branches in M001 and X006.
2.2 Design and Implementation of the Instruction List Compiler
Achieving efficient and reliable compilation of PLC programming languages is a crucial task in the research and development of embedded PLC systems. Traditional development methods involve developing a dedicated PLC instruction compiler using a high-level language. This requires writing recognition and corresponding processing programs for each program word and rule, resulting in a large workload, long development cycle, susceptibility to oversights, and poor maintainability. To improve software development efficiency, ensure software quality, and enhance maintainability, a general-purpose compiler, Lex8LYacc, is used to develop a PLC instruction compiler.
2.2.1 Introduction to Lex & Yacc
Lex8LYacc is an automatic lexical and syntax analyzer generator developed by Bell Labs in the United States using the C programming language. It is one of the most widely used compiler software programs. Lex is the lexical analyzer generator, and Yacc is the syntax analyzer generator. They can automatically convert user-provided lexical and syntax specification files into source code for various high-level languages, such as C or C++.
2.2.2 Overall Compiler Structure
The term "pass" refers to the process of scanning the source program or its equivalent intermediate language program from beginning to end and completing the specified task. The compilation process of this system includes three passes: lexical analysis, syntax analysis, and code conversion.
2.2.3 Lexical Analyzer Design
The instruction list source program can be simply viewed as a multi-line string. The lexical analyzer scans the source program character by character from top to bottom and left to right, generating tokens and transforming the string source program into an intermediate program of token strings for subsequent syntax analysis.
The lexical analyzer of this system has two working states: one is to scan the source program from beginning to end and check for all lexical errors; the other is to scan the source program from beginning to end when there are no lexical errors and input the identified word symbols to the grammar.
2.2.4 Parser Design
(1) Syntax description of PLC instruction list language
Analyzing the PLC instruction program structure extracts the structural information hidden in the instruction code. This information often implicitly expresses the operation instructions. For example, the instruction OR/ORB corresponds to a parallel structure in the ladder diagram, while AND/ANB corresponds to a series structure in the ladder diagram.
The grammar of some PLC instruction statements is described in Backus normal form as follows:
Following the yacc syntax rules, after writing the yacc source program corresponding to the Backus normal form description, use the "yacc-dvplcil . y" command to convert it into the C language source program yyparse for the parser.
(2) Convert the PLC instruction table into binary code
The binary file format of the PLC instruction list source program is as follows: each instruction's binary code occupies 32 bits. The operator's code and the component's code are added together to form the high 16 bits of the target code, and the low 16 bits are the component's number. For example, the code for the operator LD is 0xFF00, the code for component X is 0x01, and the code for the instruction LDX1 is 0xFF010001.
The code transformation function of the instruction list compiler is implemented by the action part of the yacc source program rules. When the parser recognizes a complete instruction, it saves its corresponding binary code to a file.
(3) Convert the PLC instruction list into a tree structure
The Yacc parser works by searching for rules that match the tokens seen so far. Yacc creates a set of states during parsing, each reflecting a possible position within one or more partially parsed rules. As the parser reads tokens, it pushes a token representing an incomplete rule onto an internal stack and switches to a new state reflecting the token it just read. This action is called shifting. When it finds all the symbols that make up the right side of a rule, it pops the right-hand symbols from the stack and pushes the left-hand symbols onto the stack, switching to a new state reflecting the new symbols on the stack. This action is called reduction. When Yacc reduces a rule, it executes the user code associated with that rule.
This paper utilizes the concept of a stack to convert instruction list language to a ladder diagram tree structure. A custom stack, `Stack`, is defined to push and pop pointers to objects of type `LadderElement`. During code conversion, the actions of the `Stack` differ from those of the syntax analysis stack. When `yacc` parses instructions containing elements, such as `LD/LD1` or `AND/ANI`, these elements are pushed onto the stack (as shown in lines B and C of the code above). The construction of the logic block is implemented in the action part of its corresponding syntax rule.
2.3 Design and Implementation of the Execution Module
2.3.1 Derivation of Logical Operation Algorithm
The following is a simple PLC program to illustrate the derivation process of the logic operation algorithm:
①LDX1
②0RX6
③ORIM1
④OUTY5
⑤LDIY5
⑥ANDX7
⑦ORM2
⑧ANIX10
⑨0RIM3
⑩OUTM4
⑩END
Define the OR operation of OR, ORI, and ORB as addition "+", the AND operation of AND, ANI, and ANB as multiplication "*", and the NOT operation as "［］". Then the outputs Y5 and M103 in the above program listing are respectively equal to:
All operators in the above expression will only connect two variables or one variable and one expression. Since the scanning process is executed sequentially, a computation stack can be built for the above calculation process. An incrementing stack is built, and the changes in the calculation process and the data in the stack are listed in Table 1.
2.3.2 Implementation of the execution module
The execution module of this system is implemented by the real-time thread module of RTLinux, which runs in kernel mode. The execution module is loaded immediately upon system boot and copies the PLC's binary code from the file to shared memory. The execution module interprets the binary code of the PLC instruction table in shared memory and completes the control of the switch quantities according to the logic input by the user. The workflow is shown in Figure 8.
3. Summary
The most prominent feature of embedded soft PLCs is that they utilize the hardware platform of embedded systems to implement the functions of standard PLCs in software, replacing dedicated controllers. This results in an open structure, short development cycle, low cost, and promising application prospects. Although the PLC instructions used in this paper are from the Mitsubishi FX2N programmable controller series, they can be easily modified for use with products from other manufacturers. Currently, this embedded soft PLC has been successfully applied in CNC milling machines, fully meeting control requirements.
