Abstract: This paper discusses a control algorithm for a chained static var generator (SVG) based on a cascaded H-bridge unit voltage source inverter hardware. The algorithm employs synchronous rotating current conversion (SRC) to detect the load command current, and utilizes PID ramp control and current parallel vector superposition feedback voltage equalization control strategies. A 36-channel PWM generator is constructed using a DSP+FPGA architecture to achieve a modular design of the cascaded H-bridge SVG. Based on theoretical analysis, the proposed control scheme is verified through simulation.
1 Introduction
In power systems, the large number of motor loads and other electrical equipment has led to a decline in power grid quality, characterized by low power factor and large voltage fluctuations. In recent years, the widespread use of power electronic equipment such as frequency converters and rectifiers has resulted in severe harmonic pollution of the power grid. In power grids with high industrial loads, daily power consumption is enormous, and the loads are nonlinear and impulsive, causing various power quality problems, including low power factor, high harmonic content, three-phase imbalance, power surges, voltage flicker, and voltage fluctuations. In summary, harmonic and reactive power problems in the power grid are becoming increasingly prominent, posing significant risks to the safe operation of the entire power supply and distribution system. Therefore, power systems worldwide have adopted SVC (Static Var Compensator) and APF (Analog and Positive Voltage Filter) devices in recent years to improve power grid quality. As the next generation of SVC, SVG (Static Var Generator) offers superior performance in terms of response speed, grid voltage stabilization, system loss reduction, increased transmission capacity, improved transient voltage limits, harmonic reduction, and smaller footprint. The control strategy of the chain-type SVG static var generator involved in this patent is key to its performance.
2SVG System Overall Composition
When the AC-side reactor of the SVG is not connected to the grid, the DC-side capacitor of the device is first charged through the charging resistor to give it a certain initial value. The DC-side capacitor voltage is considered to be in a balanced state and has a steady-state voltage value. The three-phase voltage and current signals of the grid side collected on site are transmitted to the DSP chip of the main control board through the parallel port via the conditioning circuit. The DSP performs filtering and data processing to obtain the three-phase reference current and calculates the reference voltage of each corresponding output. Then, the FPGA is used to generate pulse signals for each fully controlled device in the SVG device. The main system configuration is shown in Figure 1.
2.1 The main functions of the SVG DSP algorithm program
The DSP hardware resources are initialized, primarily focusing on the DSP crystal oscillator and clock divider, CPU timers and event manager, 16-bit parallel bus ports, general-purpose I/O ports, PWM comparator registers, AD sampling interrupt registers, CAN bus registers, SCI serial ports, and other on-chip resources. Functions include SVG start/stop control, grid voltage tracking phase-locked loop, open-loop reactive power data decoupling and closed-loop power output control, and fault handling.
The bus data communication function is mainly implemented by communicating with the FPGA through a 16-bit parallel data bus, sending the modulated wave data to the FPGA for PWM wave modulation output, and using the CAN bus to realize the inter-board data communication function between the host computer (human-machine interface) and other control boards.
Research on 3SVG Control Strategies
3.1 Load Reactive Power Compensation Command Current Generation Strategy
The compensation performance of an SVG static var generator is determined by the load command current detection algorithm. Common command current detection algorithms include instantaneous reactive power theory algorithms, FBD (Fryze Buchholz Depenbrock) method, SRF synchronous rotating transformation theory algorithms, and neural network control algorithms. The synchronous rotating transformation theory algorithm is based on synchronous rotating dq coordinate current transformation. First, the three-phase load current is de-zeroed (balance condition compensation). Then, Park transformation is performed to obtain the positive-sequence d-axis active power and q-axis reactive power. The d-axis active power is then passed through a low-pass filter (LPF algorithm) to obtain a harmonic-free d-axis. The q-axis reactive power is set to 0 and combined with the harmonic-free d-axis for inverse Park transformation to generate the three-phase positive-sequence active power fundamental. Subtracting the three-phase positive-sequence active power fundamental from the three-phase user load instantaneous waveform yields the three-phase positive and negative-sequence reactive power and harmonic command currents (IHaIHbIHc) that need compensation. These are then fed into the PID closed-loop control loop along with other control components. Figure 2 shows the load reactive power compensation command current generation strategy structure.
The vector i rotates counterclockwise at the fundamental frequency ω of the power grid. The synchronous rotational transformation of the load current dq can be derived using the following formula:
Based on the above analysis, the axis with a cosine relationship to θ is essentially the active axis. The q-axis is active, while the d-axis is lagging and reactive. Changing the value in the above formula will change the starting angle of the dq transformation. The output of the single-locked loop is id, iq, ω, and θ, and at this time θ = r (i.e., the d-axis coincides with the Im-axis).
3.2 DC Voltage Equalization Control Strategy for Chain-Type SVG Static Var Generator
The basic idea of the DC voltage equalization control strategy for a chain-type SVG static var generator is to superimpose a vector parallel to the current direction onto each H-bridge reference voltage. Since the output voltage and current of the H-bridge are approximately 90° out of phase, superimposing this vector allows adjustment of the active power injected into each H-bridge based on the error between the DC voltage and the reference voltage, thus balancing the voltage across each capacitor. As shown in Figure 3, the difference between the voltage and the reference DC voltage, after passing through a proportional element and multiplied by the SVG's own current, yields the active component of the reference voltage. When the capacitor voltage is lower than the reference value, the active component of the reference voltage increases, thus increasing the active power injected into the H-bridge, which in turn raises the capacitor voltage. As the capacitor voltage increases, the losses in the H-bridge increase. A new equilibrium is reached when the losses in the H-bridge equalize the injected active power.
3.3 Ramp PID Control Strategy for Chain-Type SVG Static Var Generator Startup
When a chain-type SVG static var generator starts up, after the pre-charge circuit bypass switch is closed, the main controller will turn on the IGBT. At this time, the voltage on the DC capacitor will rise according to the set value. However, since the difference between the pre-charge DC voltage and the set voltage is often large, the set voltage is generally 200V~500V higher than the pre-charge voltage. At this time, due to the small short-circuit impedance of the line (pre-charge has been bypassed), the high voltage difference will generate a large overcurrent in the main circuit. Conventional DC voltage PID cannot quickly adjust and control the error, so the overcurrent time will be relatively long (generally lasting for tens of milliseconds). The overcurrent will have an adverse effect on power devices such as IGBTs, and in severe cases, it will cause damage to the IGBTs. Therefore, it is necessary to process the DC voltage regulation during the startup process. The method we use here is to perform a ramp processing on the DC voltage set value.
The specific method is as follows: Assume the DC voltage at the moment of pre-charging completion is , and the final set value of the DC voltage is . Then the DC voltage difference between them is . We will divide this difference equally according to experience, i.e., N. Here, N can be selected based on the magnitude of the voltage difference and the final response speed of the PID controller. Then, the DC voltage establishment and adjustment after pre-charging by turning on the IGBT becomes the following relationship:
We can see that due to its existence, the adjustment process will be very smooth. By adjusting the value of N, the slope of the slope adjustment can be easily changed, improving the impact response problem of DC voltage regulation. The change in voltage regulation rate will ultimately affect the current rise rate. Based on the overall closed-loop regulation effect of the SVG system, the overcurrent degree of the start-up transient will be greatly improved, enhancing the robustness of conventional PID regulation.
3.4 Overall Closed-Loop Control Strategy for Chain-Type SVG Static Var Generator
The chain-type SVG static var generator adopts a direct current control scheme as shown in Figure 4. The main controller DSP performs AD sampling on the three-phase grid voltage (Usa, Usb, Usc), the three-phase load current (ILa, ILb, ILc), and the DC voltage of each unit.
(1) Enter the PLL phase-locked processing algorithm to perform PARK transformation on the grid voltage, and use the PI controller to track and adjust the error angle, and then obtain the sine/cosine value of the phase-locked angle of the grid voltage (and).
(2) The load command current detection algorithm performs reactive power extraction calculation on the user load current. First, the three-phase load current is processed to remove zero sequence (balance condition compensation). Then, Park transformation is performed to obtain positive sequence d-axis active power and q-axis reactive power. Then, the d-axis active power is passed through a low-pass filter (LPF algorithm) to obtain a harmonic-free d-axis. Then, the q-axis reactive power is set to 0 and together with the harmonic-free d-axis, the inverse Park transformation is performed to generate the three-phase positive sequence active power fundamental wave.
(3) The three-phase positive sequence active fundamental wave is obtained by subtracting the three-phase positive and negative sequence reactive and harmonic command currents (IHaIHbIHc) from the instantaneous waveform of the three-phase user load. The single-phase reactive command current is then entered into the reference modulation wave generation algorithm for reference modulation wave generation. In this algorithm module, the average voltage of each phase (the average value is taken after sampling 12 units per phase) is first passed through the PID processing module with the function of starting process ramp (reference target is 800V) to obtain the equivalent device active loss current amplitude.
(4) The cosine obtained by phase-locking with the grid voltage is multiplied to obtain the AC instantaneous current waveform. Then, it is summed with the instantaneous current waveform of the negative device output (the negative sign is related to the output direction of the compensation current. We assume that the current inflow direction of the device is positive and the output is negative) to form the equivalent instantaneous active current of the device. Then, it is proportionalized and then summed with the single-phase reactive command current to form the compensation command current.
(5) In order to obtain a reference modulation wave with a suitable modulation ratio, the compensation command current needs to be divided by half of Udc (normalization processing). After proportional limiting, a single-phase reference modulation wave data (PWMref) is formed. In order for the SVG to perform stable compensation operation, the DC bus voltage equalization processing of all units in each phase is also required. We use the PI error control voltage equalization algorithm between the single bus Udc and the average value. That is, the Udc collected from each individual unit is used as a feedback control signal, and then the average voltage of Udc calculated by the single phase is used as a reference for PI error adjustment. Finally, the DC bus voltage of each unit tends to be stable and balanced. In order to make the output of the voltage equalization PI error adjustment accurately modulated, the output of the error needs to be divided by the output current value of the device.
(6) The new error modulation waveform is then combined with the reference modulation wave data (PWMref) of three single phases to form the sinusoidal modulation wave data of the device. Finally, the PWM wave is generated by the PWM wave generation logic (using the multiplexed SPWM wave generation scheme) and then the IGBT power circuit of the H bridge is driven by the drive circuit to finally realize the reactive harmonic compensation function of the SVG as a whole.
4 FPGA Controller Design
The FPGA operates according to the communication protocol specified by the DSP. After the DSP completes data acquisition and algorithm processing, it sends the output modulation signal (three-phase sinusoidal modulation wave) and control signal data to the FPGA via RAM writing. The FPGA receives the data, latches it, and compares the voltage modulation signal of each phase with its own generated phase-shifted carrier wave before outputting a PWM wave.
4.1 FPGA Software Design Flowchart
Figure 5 illustrates the FPGA data and signal processing flow.
4.2 FPGA Module Design
4.2.1 Data Extraction (Caiyang_data module)
The DSP communicates with the FPGA to filter out garbled signals. As shown in Figure 6, at the FPGA receiver's CARE port, garbled data streams can be seen mixed in with the data. Median filtering is used to extract the useful data, resulting in the valid IA data stream.
4.2.2 Reading data from the internal dual-port RAM, as shown in Figure 7.
4.2.3 Separate Data Sets
The three-phase voltage signal and start/stop signal are separated (lvbo1 module). The fundamental frequency of each phase is in Q format, which is converted into an integer by the data_Qtoint module, as shown in Figure 8.
4.2.4 PLL frequency multiplier
The FPGA's built-in PLL module is used to increase the FPGA's clock speed, thereby increasing the internal carrier frequency of the FPGA. This is achieved by using the fen_pin_qi module to output the carrier clock frequency and the zaibo_Ua module to implement the carrier counting step size in parallel.
As shown in Figure 9.
4.2.5 Three-phase carrier phase shift
For parallel units in phase, the fundamental frequency is the same. The carrier generated in the FPGA is phase-shifted at a fixed angle to satisfy one cycle of the fundamental frequency. This is equivalent to multiplexing the SPWM, as shown in Figures 10 and 11.
4.2.6 FPGA PWM Output
After SPWM, the PWM output is synchronized with the system clock and controlled by the DSP's enable data, achieving controllable output. As shown in Figure 12.
5. Simulation and Experiment
5.1 Simulation Scheme and Simulation Results
To test the operation of the control system, this paper conducted an experiment on a 6kW low-power experimental platform. Each phase of the power section of the platform consists of two power units connected in series, with an AC rated voltage of 380V.
Figure 13 shows the experimental waveforms demonstrating the effect of low-pass filter compensation. The system uses PI algorithm control, with an output voltage frequency of 50Hz. In the figure, Ua is the actual sampled voltage, Ua_ref is the reference voltage calculated for this cycle, and Ua_comp is the result after compensation for Ua. Ua is obtained by DSP sampling through the voltage Hall effect sensor, low-pass filter, and voltage signal on the control board, while Ua_ref and Ua_comp are calculated by the DSP. The sampling rate is the main interrupt operating frequency of 2kHz. As can be seen from the figure, Ua and Ua_ref have significant amplitude and phase errors, while Ua_comp is close to the given signal Ua_ref in both amplitude and phase. The phase delay between them is due to the fact that in the digital control system, the calculation result for this cycle can only be issued in the next control cycle.
Figures 14 and 15 show the voltage and current waveforms under no-load and 80% load conditions at a set frequency of 1Hz. The current is sampled using a current probe connected to channel 1 of the oscilloscope. The probe's response frequency is DC-50MHz, and the sampling ratio is 1A displayed on the screen corresponding to 10A of actual current. The voltage waveform is the result of a Hall sensor connected to channel 2 of the oscilloscope. The Hall sensor's response frequency is DC-500kHz, and the sampling ratio is 1V displayed on the screen corresponding to 200V of actual voltage. It can be seen that the motor operates stably at low speeds.
Figures 16 and 17 show the voltage and current waveforms under no-load and 80% load conditions when the operating frequency is set to 40Hz. The voltage and current ratios are the same as at 1Hz. At this time, the voltage waveform is closer to a sine wave, demonstrating the advantages of a multi-level inverter.
6 Conclusions
The use of cascaded H-bridge SVG as the core structure has become a major trend in the future research and development of reactive power compensation. Researching more reliable current tracking control methods and DC-side capacitor voltage balance control strategies is of significant research importance and application potential for improving the dynamic response and reliability of SVG during harmonic suppression. An experimental verification platform was built using FPGA to demonstrate the effectiveness of the proposed control scheme. The reliability of the control scheme was verified through experiments on a low-power platform.
