The 74LS148 is an 8-3 line priority encoder with expansion capabilities. It has 8 signal inputs, 3 binary code outputs, one input enable, one strobe output, and one expansion terminal. The chip is selected when the enable is "0"; otherwise, it is not selected. The strobe output and expansion terminal are mainly used for functional expansion.
1. Introduction to 74LS148
Figure 1 shows the logic symbol of the 74LS148, where I′0-I′7 are 8 signal input terminals, Y′2-Y′0 are 3 binary code output terminals, S′ is the input enable terminal, Y′S is the strobe output terminal, and Y′EX is the expansion terminal. Its logic function table is shown in Table 1.
Table 1 Logic Function Table of 74LS148
In Table 1, Χ represents any number between 0 and 1. As can be seen from Table 1, the encoding inputs I′0-I′7 are active low, with I′7 having the highest priority and I′0 having the lowest priority. When the enable terminal S′ is “0”, the chip is selected; otherwise, it is not selected. When the circuit is in the disabled state, Y′SY′EX = 11; when the circuit is in the working state, Y′SY′EX = 10; and when the circuit is in the working state but has no encoding input, Y′SY′EX = 01.
2. Use two 74LS148 chips to construct a 16-4 line priority encoder.
Two 74LS148 chips have 16 input terminals and can be configured as a 16-4 line priority encoder . When configuring a 16-4 line priority encoder, I′0-I′7 of the lower-order chip 74LS148 (1) are used as the lower 8 bits A′0-A′7 of the encoder, and I′0-I′7 of the higher-order chip 74LS148 (2) are used as the higher 8 bits A′8-A′15 of the encoder. The 16-4 line priority encoder should have 4 output terminals. The Y′EX terminal of 74LS148 (2) can be connected to a NAND gate. The output of the NAND gate... The two chips are connected to the Z3 output of the 16-4 line priority encoder. The Y′2 terminals of the two chips are connected to the input of the NAND gate, and the output of the NAND gate is used as the Z2 output of the 16-4 line priority encoder. The Y′1 terminals of the two chips are connected to the input of the NAND gate, and the output of the NAND gate is used as the Z1 output of the 16-4 line priority encoder. The Y′0 terminals of the two chips are connected to the input of the NAND gate, and the output of the NAND gate is used as the Z0 output of the 16-4 line priority encoder. The S′ terminal of the high-order chip is connected to a low level. This can form a 16-4 line priority encoder. Figure 2 shows two 74LS148 chips forming a 16-4 priority encoder.
Figure 2. Two 74LS148 chips form a 16-line to 4-line priority encoder.
The working principle of Figure 2 is analyzed below: Since S′ of 74LS148(2) is grounded, it meets the requirement that S′ is low level, and 74LS148(2) is selected. When A′15＝0, Y′2Y′1Y′0＝000 and Y′SY′EX＝10 in the high-order chip, that is, Z3＝1. S′ of the low-order chip is 1. At this time, 74LS148(1) is not selected, and the low-order chip's
3. Use three 74LS148 chips to construct a 24-5 line priority encoder.
Three 74LS148 chips have 24 input terminals, which can be used to construct a 24-5 line priority encoder. When constructing a 24-5 line priority encoder, the I′0-I′7 of the lowest bit chip 74LS148 (1) are used as the lowest 8 bits of the 24-5 line priority encoder coder, A′0-A′7; the I′0-I′7 of the second lowest bit chip 74LS148 (2) are used as the second lowest 8 bits of the 24-5 line priority encoder coder, A′8-A′15; and the I′0-I′7 of the highest bit chip 74LS148 (3) are used as the highest 8 bits of the 24-5 line priority encoder coder, A′16-A′23. The 24-5 line priority encoder should have 5 output terminals. The Y′EX terminal of 74LS148 (3) can be connected through a NAND gate, and the output of the NAND gate is used as the 24-5 line priority encoder coder. The Z4 output of the encoder, the Y′EX of 74LS148 (2) and the Y′EX of 74LS148 (3) are connected to the input of the NAND gate. The output of the NAND gate is used as the Z3 output of the 24-5 line priority encoder. The Y′2 of the three chips is connected to the input of the NAND gate. The output of the NAND gate is used as the Z2 output of the 24-5 line priority encoder. The Y′1 of the three chips is connected to the input of the NAND gate. The output of the NAND gate is used as the Z1 output of the 24-5 line priority encoder. The Y′0 of the three chips is connected to the input of the NAND gate. The output of the NAND gate is used as the Z0 output of the 24-5 line priority encoder. The S′ of the high-order chip 74LS148 (3) is connected to a low level. In this way, a 24-5 line priority encoder can be constructed. Figure 3 shows a 24-5 line priority encoder constructed by three 74LS148 chips.
Figure 3. A 24-5 line encoder composed of three 74LS148 chips.
Based on the above analysis, this logic circuit encodes the input low-level signals A′0–A′23 into 00000–10111, where A′0 has the lowest priority and A′23 has the highest priority. Therefore, this circuit can realize the logic function of a 24-to-5 line priority encoder. Since there are 5 output terminals, they can be represented by 5-bit binary codes. There are 32 possible combinations of 5-bit binary codes. We can choose any 24 of these 32 combinations to encode A′0–A′23. Depending on the selection, different encoding methods can be formed, thus obtaining different logic circuits that realize the logic function of a 24-to-5 line priority encoder. Alternatively, three 74LS148 chips can be used to construct 23-to-5 line, 22-to-5 line, 21-to-5 line, and 20-to-5 line encoders. When constructing a 23-to-5 line priority encoder, simply connect A′23 in Figure 3 to a high level. When constructing a 21-to-5 line priority encoder, connect A′23 and A′22 in Figure 3 to a high level, and so on.
4. Use four 74LS148 chips to construct a 32-5 line priority encoder.
Four 74LS148 chips have 32 input terminals, which can be used to construct a 32-5 line priority encoder. When constructing a 32-5 line priority encoder, I′0-I′7 of 74LS148(1) are used as the A′0-A′7 input terminals of the 32-5 line priority encoder coder, I′0-I′7 of 74LS148(2) are used as the A′8-A′15 input terminals of the 32-5 line priority encoder coder, I′0-I′7 of 74LS148(3) are used as the A′16-A′23 input terminals of the 32-5 line priority encoder coder, and I′0-I′7 of 74LS148(4) are used as the A′24-A′31 input terminals of the 32-5 line priority encoder coder. The 32-5 line priority encoder should have 5 output terminals. The Y′EX terminals of 74LS148(3) and 74LS148(4) can be connected to the input terminals of a NAND gate. The output of the NAND gate is used as the Z4 output of the 32-5 line priority encoder. The Y′EX of 74LS148 (2) and the Y′EX of 74LS148 (4) are connected to the input of the NAND gate. The output of the NAND gate is used as the Z3 output of the 32-5 line priority encoder. The Y′2 of the four chips is connected to the input of the NAND gate. The output of the NAND gate is used as the Z2 output of the 32-5 line priority encoder. The Y′1 of the three chips is connected to the input of the NAND gate. The output of the NAND gate is used as the Z1 output of the 32-5 line priority encoder. The Y′0 of the three chips is connected to the input of the NAND gate. The output of the NAND gate is used as the Z0 output of the 32-5 line priority encoder. The S′ of the high-order chip 74LS148 (3) is connected to a low level. In this way, a 32-5 line priority encoder can be constructed. Figure 4 shows a 32-5 line priority encoder constructed by four 74LS148 chips.
Figure 4 shows a 32-line to 5-line priority encoder constructed using four 74LS148 chips.
In the logic circuit of Figure 4, the circuit encodes the input low-level signals A′0-A′31 into 00000-11111, where A′0 has the lowest priority and A′31 has the highest priority. Therefore, the circuit can realize the logic function of a 32-5 line priority encoder. Its working principle analysis is similar to that of a 24-5 line decoder.
5. Conclusion
The above provides an introduction and analysis of cascading four or fewer 74LS148 chips. The design and analysis of cascading more 74LS148 chips can be carried out in the same way. It can be seen that when different 74LS148 chips are cascaded, there can be multiple input signals requesting encoding, but the encoder only encodes the highest priority signal. Only when the input terminal with the highest priority is an invalid signal will the signal with the lower priority be encoded.
