A rotary encoder is a high-precision angular position measurement sensor with high resolution and fast response speed. It is widely used in control systems that use position or angle as the object. The encoder is installed on the non-load end of the motor shaft and rotates with it. Its feedback signal is transmitted to the controller to form a closed-loop control of the motor [1].
An incremental rotary encoder outputs two orthogonal pulses, namely two square waves (A and B) with a 90° phase difference. Their phase relationship indicates the direction of motor rotation. When phase A leads phase B by 90°, the motor rotates forward, as shown in Figure 1; when phase B leads phase A by 90°, the motor rotates in reverse, as shown in Figure 2. The encoder outputs a fixed number of pulses per revolution. By accumulating the pulse counts of phases A and B, the angle rotated by the motor can be calculated.
This paper designs an interface circuit for an incremental rotary encoder using VHDL, which can be configured on a CPLD or FPGA to achieve functions such as quadrupling the frequency of the encoder output signal, bidirectional reversible counting, and interfacing with a microcontroller. The design principles and implementation source code of each circuit are introduced below.
1. Design principle of a quadruple frequency multiplier circuit
For each given encoder , the angular displacement corresponding to its pulse period T is fixed at q, and its quantization error is q/2. If the frequencies of signals A and B are quadrupled, the period of the counting pulse will be reduced to T/4, and the quantization error will be reduced to q/8, thereby improving the angular displacement measurement accuracy by 4 times [2].
As shown in Figures 1 and 2, within any period T, signals A and B each change twice, generating one rising edge and one falling edge respectively. If Y is used to count the transition edges of signals A and B, then within one pulse period, signal Y will change 4 times, achieving a fourfold frequency multiplication of the encoder signal.
2. Steering Discrimination Circuit Design Principle
The direction of rotation can be determined by detecting the level of the other phase signal at the rising edge of the signal [3]. For example, the level of the B phase signal is detected at the rising edge of the A phase signal. If B is low (as shown in Figure 1), it indicates that the motor is rotating in the forward direction; if B is high (as shown in Figure 2), it indicates that the motor is rotating in the reverse direction. Based on the four-fold frequency multiplication principle mentioned above, the counting rules are summarized as follows.
(1) The following state indicates that the motor is rotating forward, so increment the counter:
① Rising edge of phase A, B=0; ② Falling edge of phase A, B=1; ③ Rising edge of phase B, A=1; ④ Falling edge of phase B, A=0.
(2) The following state indicates that the motor is reversing, so the count is decremented:
① Rising edge of phase B, A=0; ② Falling edge of phase B, A=1; ③ Rising edge of phase A, B=1; ④ Falling edge of phase A, B=0.
3. Interface Design Principles with Microcontroller
The pulse count value of the encoder is usually transmitted to the microcontroller or other controller for processing. However, the frequency of the global clock of the CPLD is higher than that of the microcontroller. In order to ensure the correctness of the transmission of the count value between the CPLD and the microcontroller, the microcontroller first sends a signal to the CPLD to latch the count value before transmitting it. The interface diagram between the CPLD and the microcontroller is shown in Figure 3. In this design, the CPLD latches the current count value after detecting the rising edge of the microcontroller's latch signal [4]. Then, the CPLD transmits the high 8 bits and low 8 bits of the 16-bit count value to the microcontroller's 8-bit I/O port in a time-division manner at the rising and falling edges of the microcontroller's bit selection signal.
4. Source code for implementing the circuit
This design utilizes the delay function of a D flip-flop to detect signal transition edges. When a pulse signal is connected to the D input, the Q output reflects the pulse signal state of the previous CLK cycle. At the rising edge of CLK, the design checks whether the Q output and D signal levels are consistent; inconsistency indicates a transition edge has occurred.
Let A and B be the source signals of phases A and B, respectively. After passing through a D flip-flop, the phase signals of phases A and B are denoted as A1 and B1. Then the counting rule is expressed as:
5 Simulation Results
Using ALTERA's development tool MAX+PlusⅡ, input a VHDL text file, the target device is EPM7128SLC84[5], the CLK period is 200ns, and the periods of A and B are 2000ns. The simulation waveforms after compilation are shown in Figures 4 to 7.
Figure 4 shows the simulated waveform when the encoder is rotating forward. Within one cycle of the A phase signal, the count value OUTPUT increases from the initial value of 4 to 8 within the two marker lines, achieving a fourfold frequency multiplication count.
Figure 5 shows the simulated waveform when the encoder reverses. Within one cycle of the A phase signal, the count value OUTPUT decreases from the initial value of 15 to 11, achieving a fourfold frequency reduction count.
Figure 6 shows the simulation waveform when the encoder switches from forward to reverse. As indicated by the marked line in the figure, when phase B leads the first rising edge of CLK after phase A, the counting direction immediately changes from incrementing to decrementing.
As shown by the marked lines in Figure 7, the 16-bit count value is latched in OUT_lock at the rising edge of the latch signal lock; at the first rising edge of CLK after the rising edge of the bit selection signal choose, the 8-bit count value OUTPUT8 outputs the high 8 bits of OUT_lock; at the falling edge of choose, OUTPUT8 outputs the low 8 bits of OUT_lock.
As can be seen from the simulation waveforms above, the design of this circuit realizes the functions of encoder direction identification, frequency quadrupling, bidirectional counting, and communication with the microcontroller.
The encoder interface circuit designed in this paper has a simple structure and high reliability, and can work with high precision even in situations where forward and reverse rotations frequently switch. This interface circuit has been applied in a single-stage rotating inverted pendulum control system and is operating well.
