Introduction
AllegroMicroSystems current sensor ICs can be categorized into three main types: sensors requiring an external magnetic core, sensors with a built-in magnetic core, and sensors with an integrated current-carrying ring (but no magnetic core). The last category is sensors with common-mode field rejection (CMR) functionality. This article will explore the mechanism of CMR and focus on how to leverage this mechanism to optimize circuit board design and layout.
background
In ICs using integrated current-carrying rings, the current-carrying rings can generate a magnetic field that the IC can measure. This magnetic field is converted into a voltage via the Hall effect. This Hall voltage is proportional to the magnitude and direction of the current. Figure 1 shows an example of a magnetic field generated by the lead frame of a specific current sensor IC. In this figure, the arrows indicate the current passing through the lead frame, and the color plot represents the magnetic field generated when 100A of DC current passes through the sensor. For clarity, the current source has been removed from the figure.
Figure 1: Magnetic field of the ACS780 current sensor lead frame.
Using an IC with an integrated current-carrying ring offers many advantages: no magnetic core required, virtually no hysteresis, low power consumption, and high temperature accuracy. However, due to the absence of a magnetic core, the sensor is susceptible to stray magnetic fields generated by magnets or current in the conductors surrounding the sensor IC. To suppress stray magnetic fields, many Allegro current sensors incorporate a dual Hall common-mode suppression scheme. The Hall plates are arranged to ensure that the field polarity induced by each Hall plate is opposite when current passes through the IC's integrated conductor or current-carrying ring. In Figure 1, the positions of the two Hall plates are denoted by H1 and H2. As can be seen from the figure, these two regions have magnetic fields in opposite directions.
The basic principle of CMR technology is that if the signals from the two Hall plates are subtracted, the signals induced by the integrated circuit can be summed, thus suppressing any stray magnetic field common-mode (unipolar) signals entering the IC. For example, assuming the magnetic fields ±B of each Hall plate are equal in magnitude but opposite in direction, then:
H1–H2∝B1–B2
B–B2 = B–(–B)
B – (–B) = 2 × B
therefore,
H1–H2 ∝ 2×B
Assuming that the two Hall plates have equal stray magnetic fields Bext, then:
H1–H2∝B1–B2
B1–B2＝（B＋Bext）–（–B＋Bext）
(B+Bext)–(–B+Bext)=2×B+Bext–Bext
2×B＋Bext–Bext＝2×B
therefore,
H1–H2 ∝ 2×B
Allego's other technical document, "Common-Mode Field Suppression Technology for Coreless Hall Effect Current Sensor ICs," provides a more detailed introduction to the theory and guiding equations of CMR technology. This article primarily introduces how to design and arrange the current-carrying circuitry of these current sensor ICs. Furthermore, this article also provides guidelines for minimizing other stray sources.
Magnetic field generated by nearby current
To fully utilize the CMR capabilities of these devices, the circuit board containing the IC should be designed so that the external magnetic fields of the two Hall plates are identical. This helps minimize errors caused by the external magnetic field generated by the current-carrying PCB itself. Three key parameters of each current-carrying trace determine the causes of IC errors: the distance from the IC, the width of the current-carrying trace, and the angle between it and the IC. Figure 2 shows an example of current-carrying traces near the IC. The distance d between the device and the conductor is the distance between the center of the device and the center of the conductor, the current path width is w, and the angle θ between the device and the current path is the angle between the straight line connecting the two Hall plates and the perpendicular line of the current path.
Figure 2: ACS780 with adjacent current path (viewed from the bottom of the sensor).
The position and orientation of the two Hall effect sensors vary depending on the IC. For example, as shown in Figure 3, the Hall effect sensor of the ACS724 is rotated 90° compared to that of the ACS780. When routing current paths near any Allegro current sensor IC with CMR functionality, it is best to keep θ as close to 90° as possible.
Figure 3: ACS724 current sensor IC with Hall plate aligned.
If it is not possible to keep θ close to 90°, the next best option is to keep the distance d between the current path and the current sensor IC as large as possible. Assuming the worst angle between the current path and IC, i.e., θ = 0° or 180°, see the following equation:
Here, H distance is the distance between the two Hall plates, and Cf is the IC coupling factor. This coupling factor varies depending on the IC. The coupling factor of the ACS780 is 5 to 5.5 G/A, while the coupling factor of other Allegro ICs ranges from 10 to 15 G/A.
Error estimation
Equation 1 assumes an infinitely long and infinitely thin conductor. It does not consider the width and thickness of the current-carrying conductor. Figure 4 shows the current-carrying error calculated using the ACS780 in the worst-case direction (θ = 0° or 180°). This error is calculated using the ideal equation and a computationally dense set of equations that consider the conductor width and thickness. The figure shows that the calculated error is higher than the result using the ideal equation. Therefore, Equation 1 can be used for a fast and conservative estimation of the error.
Figure 4: Error calculated using ideal equation 1 versus using trajectory dimensions in ACS780.
More precise calculation methods can be used to calculate the error for current paths of varying widths and different angles between the device and the current path. For all angles and widths, it is assumed that a 4-ounce copper conductor is used to set the current path thickness. The figure shows that the current carrier width affects the error, but the biggest influencing factors are the angle θ with respect to the device and the distance d from the device.
Figure 5: Errors caused by ACS780 calculation of 4-ounce copper conductor traces; multi-trace widths θ = 0° and 60°
Other layout principles to consider
When laying out a circuit board containing an Allegro current sensor IC with CMR, the orientation and proximity of all current-carrying paths are important factors, but other factors must be considered to optimize IC performance. Other stray field sources that may affect system errors include traces connected to the IC's integrated current carrier and the location of nearby permanent magnets.
The connection between the circuit board and the current sensor IC must be carefully planned. Common mistakes that can affect performance include:
● Angle of approach from the current path to the IP pin
● The current trace extends too far below the IC.
Approach angle
A common mistake when using Allegro current sensor ICs is using an inappropriate current introduction angle. Figure 6 shows an example of a current trajectory approaching an IC (here, the ACS724). This figure shows the trajectories for IP+ and IP–. The light green area is the ideal approach zone for IP+. This zone ranges from 0° to 85°. The same rule applies to the IP– trajectory.
This area is restricted to prevent current-carrying traces from affecting any stray fields that could cause errors in the IC output. If a current trace connected to the IP is outside this area, it must be handled as described above (magnetic field caused by adjacent current paths).
Figure 6: The ideal range of the ACS724 current trace for the angle θ is 0° to 85°, which is likely different from other Allegro current sensor ICs.
IC-based extensions
Another common mistake is placing current traces too far from the IP pins. Depending on the device, this can lead to two different problems. For SOIC and similar packages, this can cause stray fields on the IC, degrading performance. For LR packages, because the IP bus is large and exposed, excessively long traces under the package can alter the current path through the IP bus, thus changing device performance. The impact on LR packages will be discussed in more detail below.
The problem is exacerbated by stray fields if current traces enter the IP bus at an angle. In this case, the current actually flows under the device, away from the IP pin, and then upwards through the pin. This altered current path can lead to stray fields, reducing IC accuracy. Preventing current traces that extend from under the device to the IP pin will prevent this.
Figure 7: When the ACS724 is extended below the IC, the current trace is too far below the IC, which changes the current path and reduces accuracy.
Permanent magnet influence
If a permanent magnet is placed near a current sensor IC, the stray field caused by the magnet will also affect the IC's performance. Generally, the stray field from the magnet can vary greatly depending on the magnet itself. It depends on the magnet's size, material, magnetization direction, and many other factors. If the current sensor can be adjusted so that the Hall plate is perpendicular to the magnet (as shown in Figure 8), the effects of these stray fields can be minimized.
Figure 8: ACS780 with the optimal orientation near the permanent magnet.
LR encapsulates specific layout rules
IC-based extensions
In LR packages, the extended current-carrying traces beneath the device effectively alter the path of current through the IP bus. This can change the coupling factor between the IP bus and the IC, significantly reducing device performance.
The ANSYS Maxwell electromagnetic suite can be used to simulate current density and the magnetic field generated by the current. Figure 9 shows the results of two different simulations. The first case is where the current trajectory leading up to the IP bus terminates at the desired point. The second case is where the current trajectory extends too far above the IP bus. The red arrows in both simulations indicate regions of high current density. In the simulation without excessive overlap (red area), the current density differs significantly from that in the simulation with excessive overlap. It can also be seen that the H1 field is larger than when there is less overlap. This is indicated by a blue shading.
Figure 9: Simulation of ACS780 leadframe with different current traces and IP bus overlap.
Excessive overlap can lead to other problems, such as a significant reduction in the current approach angle range. If the current trace extends too far across the IP bus, it creates a dependency on the approach angle, meaning the approach angle directly affects the device's coupling factor. The best way to avoid this is to limit the overlap of current traces.
Figure 10: ACS780 PCB layout reference. Make necessary adjustments to meet application process requirements and PCB layout tolerances, and highlight the critical dimensions circled in red.
in conclusion
AllegroMicroSystems current sensor ICs offer several advantages. These ICs exhibit near-zero hysteresis and very low power consumption. A drawback of being coreless is susceptibility to stray magnetic fields. However, many of these ICs are capable of suppressing common-mode magnetic fields.
CMR technology performs best when the common-mode fields of the two Hall effect sensors are equal. We explore several techniques to significantly reduce the difference in common-mode fields between the two Hall effect sensors, namely, how to route external current paths and other optimized layout techniques. For cases where current paths cannot be routed in the most advantageous direction, we also introduce error estimation. Furthermore, we discuss some layout techniques for LR packages, as certain characteristics of LR packages must be considered to achieve optimal performance.
In summary, the techniques and calculations discussed in this article help customers optimize the performance of Allegro and current sensor ICs.
