DDR Hardware Design Essentials
1. Power supplies for DDR can be divided into three categories:
The main power supply consists of VDD and VDDQ. The requirement for the main power supply is that VDDQ = VDD. VDDQ is the power supply for the IO buffer, and VDD is the power supply for the IO buffer. However, in general use, VDDQ and VDD are combined into a single power supply.
Some chips also have a VDDL, which powers the DLL and can share the same power supply as VDD. Power supply design requires consideration of whether the voltage and current meet requirements, the power-on sequence and timing, and monotonicity. The power supply voltage requirement is generally within ±5%. Current needs to be calculated based on the specific chips used and the number of chips. Since DDR generally draws a large current, ideally, the PCB design should have a complete power plane across the pins, with a large capacitor at the power input for energy storage and a small 100nF to 10nF capacitor for filtering on each pin.
The reference power supply Vref must follow VDDQ, and Vref = VDDQ/2. Therefore, it can be provided by a power supply chip or obtained using a resistor divider. Since Vref typically has a small current, in the range of a few mA to tens of mA, using a resistor divider is more cost-effective and offers greater flexibility in layout. It can be placed close to the Vref pin, closely following the VDDQ voltage, so this method is recommended. Note that the resistors used for the voltage divider can be between 100 and 10K ohms, and should have 1% precision. A 10nF capacitor should be added to each pin of the Vref reference voltage for filtering, and it's also advisable to connect a capacitor in parallel with each voltage divider resistor.
C. Tracking Termination Voltage (VTT) used for matching
VTT is the power supply pulled up by the matching resistor, and VTT = VDDQ/2. In DDR design, depending on the topology, some designs do not use VTT, such as when the controller supports a small number of DDR devices. If VTT is used, the current requirement for VTT is relatively large, so copper traces need to be laid over it. Furthermore, VTT requires the power supply to both sink and pump current. Generally, a power supply chip specifically designed for DDR to generate VTT can be used to meet these requirements.
In addition, a 10NF~100nF capacitor is usually placed next to each resistor pulled to VTT, and the entire VTT circuit needs a large capacitor in the μF range for energy storage.
In Huawei's designs, when using DDR chips, VTT power supply is almost entirely eliminated, and Thevenin matching with pull-up and pull-down resistors is used exclusively. VTT power supply is only used when using memory modules.
Generally, DDR data lines use a one-to-one topology, and both DDR2 and DDR3 have internal ODTs for matching, so good signal quality can be achieved without needing to connect to VTTs for matching. DDR2 address and control signal lines, in multi-load scenarios, may have a one-to-many configuration and lack an internal ODT, resulting in a T-shaped topology. Therefore, VTTs are often required for signal quality matching and control. DDR3 can use a fly-by routing method.
This article analyzes and compares the differences between using high-impedance load traces and using the same impedance for both the main trace and the load traces in a DDR3 design case.
As shown in the diagram above, Case 1 uses a 50-ohm impedance design from the inner controller to each SDRAM. Case 2 uses a 40-ohm design for the main line and a 60-ohm design for the load line. These are compared and analyzed using simulation tools.
As can be seen from the simulation waveforms above, Case 2, which uses a higher impedance load trace, significantly outperforms Case 1, where both the main and branch lines use the same impedance, in terms of signal quality. Furthermore, the impact is greatest on the load closest to the driver end, and less on the load furthest away from the driver end. This is precisely what was analyzed earlier: the distributed capacitance of the load causes a decrease in impedance in the load trace. If the main and load lines were designed with the same impedance, it would lead to impedance discontinuity. Designing the load trace with a higher impedance balances the distributed capacitance introduced by the load, thus achieving impedance balance across the entire trace.
Balancing load capacitance by increasing the load trace impedance is a common practice in traditional daisy-chain designs. DDR3 refers to this topology as fly-by, which is significant, emphasizing the need for sufficiently short load stub traces.
2. Clock
DDR clock signals are transmitted via differential traces, typically using a 100-ohm parallel terminating impedance. The differential pair control impedance is 100 ohms, and the single-ended impedance is 50 ohms. It's important to note that differential lines can also use series matching. The advantage of series matching is that it allows control over the rise time of the differential signal, which may have some effect on EMI.
3. Data and DQS
The DQS signal acts as a reference clock for the data signal, and its routing must maintain the same length as the CLK signal. In DDR2 and earlier versions, DQS is a single-ended signal. DDR2 can be used as a differential signal or a single-ended signal; when used as a single-ended signal, DQS- needs to be grounded. DDR3, however, is a differential signal and requires a 100-ohm differential trace. Because of the internal ODT (Optical Distribution Array), DQS does not require a 100-ohm parallel resistor for termination. Each 8 bits of data signal corresponds to one DQS signal.
When routing DQS signals, they need to maintain the same length as other DQS signals in the same group, controlling the single-ended impedance to 50 ohms. During data writing, DQ and DQS are center-aligned; during data reading, their edges are aligned. DQ signals are typically one-to-one, and DDR2 and DDR3 have internal ODT matching, so generally, series matching is sufficient.
4. Address and Control
Address and control signals are slower than DQ signals, sampling based on the rising edge of the clock, so they need to be the same length as the clock traces. However, if multiple DDR chips are used, the address and control signals operate on a one-to-many basis, so it's important to ensure the matching method is appropriate.
5. PCB Layout Considerations
When laying out the PCB, the DDR chips should be placed as close as possible to the DDR controller. Each power pin requires a filter capacitor, and the entire power supply should have a capacitor of at least 10uF at the power input. Ideally, the power supply should be placed on a dedicated layer on the pins. Series matching resistors should ideally be placed at the source end; if it's a bidirectional signal, they should all be placed at the same end. For a one-to-many DDR matching structure, the VTT pull-up resistor should be placed at the farthest end, ensuring a balanced chip arrangement. The following diagram shows several DDR topologies. First, in a one-to-two configuration, there are tree structures, daisy chains, and fly-by structures. Fly-by is a daisy chain structure with a very small stack. Daisy chain structures are suitable for both DDR2 and DDR3. A tree structure allows two chips to be mounted on opposite sides of the PCB, minimizing the length of the branches. One-to-many DDR topologies are more complex and require careful simulation.
6. PCB routing precautions
When routing on a PCB, single-ended traces should have an impedance of 50 ohms, and differential traces should have an impedance of 100 ohms.
Note that the length of differential lines should be controlled within ±10mil. The length of the same group of traces may vary depending on the speed requirements, and is generally ±50mil.
The control and address lines, as well as the DQS line and the clock line, are of the same length. The DQ data line and the DQS line in the same group are of the same length.
Note that the clock and DQS signals should be kept at least 3W away from other signals.
The signal between groups should also be at least 3W wide apart.
It is best to route the same group of signals on the same floor.
Minimize the number of vias.
7. EMI issues
Because of its high speed and frequent access, DDR memory requires consideration of external interference in many designs. The following points should be noted during the design process.
The principle is to prevent DDR from interfering with circuit modules and signals that have performance requirements and are susceptible to interference, such as analog signals, radio frequency signals, clock signals, etc., and thus affecting the performance.
The DDR power supply should not share the same power supply as other power modules that are susceptible to interference. If it is necessary to use the same power supply, be sure to use inductors, ferrite beads or capacitors for filtering and isolation.
On the clock and DQS signal lines, reserve some positions for adding series resistors and parallel capacitors. When EMI exceeds the standard, increase the series resistor or the capacitor to ground within the range allowed by signal integrity to slow down the signal rise time and reduce external radiation.
Shielding is performed using a metal casing to shield against external radiation.
Take care to maintain the integrity of the land.
8. Testing Methods
Ensure that the oscilloscope probe and the oscilloscope's bandwidth meet the testing requirements.
When selecting test points, it is important to choose them as close as possible to the signal receiving end.
Because DDR signaling is relatively complex, we want to simplify the separation of read and write bits to quickly test, debug, and resolve signal issues. In this case, eye diagram analysis is the most common method to help check whether the DDR signals meet the requirements for voltage, timing, and jitter.
There are several triggering modes. First, a preamble width trigger can be used to separate the read/write signals. According to the JEDEC specification, the read preamble width is 0.9 to 1.1 clock cycles, while the write preamble width is specified to be greater than 0.35 clock cycles, with no upper limit. The second triggering method uses a larger signal amplitude trigger to separate the read/write signals. Typically, the read and write signals have different amplitudes, so we can achieve separation by triggering the oscilloscope with a larger signal amplitude.
During testing, attention should be paid to the signal amplitude, clock frequency, differential clock crossover point, whether the rising edge is monotonic, and overshoot, etc.
The most important and crucial timeframes to consider are setup time and hold time.
