Rotary encoders are widely used in industrial automation systems. A typical application for this type of encoder is in electric machinery, where the encoder is connected to a rotating shaft to provide feedback to the control system. While the primary use of encoders is for angular position and speed measurement, other features such as system diagnostics and parameter configuration are also common. Figure 1 shows a motor control signal chain that utilizes an RS-485 transceiver and a microprocessor to connect an absolute encoder (ABS encoder) slave to an industrial servo drive master to achieve closed-loop control of an AC motor.
The RS-485 communication link between the servo drive and the ABS encoder typically requires high data rates of up to 16 MHz and low propagation delay timing specifications. The maximum RS-485 cable length is typically 50 meters, but can sometimes be as long as 150 meters. Motor control encoder applications present a challenging environment for data communication because electrical noise and long cables can affect the integrity of RS-485 signal transmission. This article highlights the main benefits of using the Analog Devices 50 Mbps (25 MHz) ADM3065ERS-485 transceiver and ADSP-CM40x mixed-signal control processor in motor control applications.
The ADM3065ERS-485 transceiver is designed to operate reliably in harsh environments such as motor control encoders and features enhanced immunity and (IEC) 61000-4-2 ESD (electrostatic discharge) robustness.
Figure 1. Using RS-485 to connect the absolute encoder slave and the servo drive master to achieve closed-loop control of the AC motor.
immunity
RS-485 signal transmission is a balanced differential transmission, inherently resistant to interference. System noise is evenly coupled to each conductor in the RS-485 twisted-pair cable. The transmission of one signal is opposite to that of another, and the electromagnetic fields coupled to the RS-485 bus cancel each other out. This reduces electromagnetic interference (EMI) in the system. Furthermore, the ADM3065E's enhanced 2.1V drive strength supports a higher signal-to-noise ratio (SNR) in communications. Adding signal isolation to the ADM3065E can be easily achieved using the ADuM141D. The ADuM141D is a four-channel digital isolator using Analog Devices' iCoupler® technology. The ADuM141D operates at data rates up to 150Mbps, making it suitable for use with the 50Mbps ADM3065ERS-485 transceiver (see Figure 2). Direct power injection (DPI) measures the device's ability to suppress noise injected into the power supply or input pins. The isolation technology used in the ADuM141D has been tested and complies with the DPIIEC62132-4 standard. The ADuM141D's immunity performance surpasses that of similar products. The ADuM141D maintains excellent performance across the entire frequency range, while other isolation products exhibit bit errors in the 200MHz to 700MHz band.
Figure 2. 50Mbps RS-485 solution with signal isolation (simplified diagram, not showing all connections)
IEC61000-4-2 ESD Performance
ESD on exposed RS-485 connectors and cables from the encoder to the motor driver is a common system hazard. The system-level IEC 61800-3 standard, related to the EMC immunity requirements of variable speed electric drive systems, requires a minimum of ±4kV (contact) / ±8kV (air) IEC 61000-4-2 ESD protection. The ADM3065E exceeds this requirement, providing ±12kV (contact) / ±12kV (air) IEC 61000-4-2 ESD protection. Figure 3 shows a comparison of the 8kV contact discharge current waveform in the IEC 61000-4-2 standard with the 8kV waveform of the Human Body Model (HBM) ESD. As can be seen from Figure 4, the waveform shapes and peak currents specified by the two standards are different. The peak current associated with the IEC 61000-4-2 8kV pulse is 30A, while the corresponding HBM ESD peak current is less than one-fifth of that value, at 5.33A. Another difference is the rise time of the initial voltage spike. For IEC 61000-4-2 ESD, the rise time is 1 ns, which is much faster than the 10 ns time associated with the HBMESD waveform. The power value associated with the IEC ESD waveform is significantly larger than the corresponding value for the HBMESD waveform. The HBMESD standard requires the device under test (EUT) to withstand 3 positive discharges and 3 negative discharges, while the IEC ESD standard requires 10 positive discharges and 10 negative discharges. Compared to other RS-485 transceivers with various nominal HBMESD protection levels, the ADM3065E, with its IEC 61000-4-2 ESD rating, is better suited for operation in harsh environments.
Figure 3. Comparison of IEC61000-4-2 ESD waveform (8kV) and HBMESD waveform (8kV)
EnDat communication protocol
Encoders use various communication protocols, such as EnDat, BiSS, HIPERFACE, and Tamagawa. Despite their differences, encoder communication protocols share similarities in implementation. These protocols interface with a serial bidirectional pipe, conforming to RS-422 or RS-485 electrical specifications. While the hardware layers are similar, the software required to run each protocol is unique. The communication stack and required application code are protocol-specific. This article primarily describes the hardware and software implementation on the host side of the EnDat 2.2 interface.
Delay impact
Delays are categorized into two types: the first is the transmission delay of the cable, and the second is the propagation delay of the transceiver. Cable delay is determined by the speed of light and the dielectric constant of the cable, typically ranging from 6 ns/m to 10 ns/m. When the total delay exceeds half a clock cycle, communication between the master and slave devices will fail. Designers have the following options in response:
Reduce data rate
Reduce propagation delay
Provide latency compensation on the host side
Option 3 compensates for both cable delay and transceiver delay, making it an effective way to ensure the system can operate at high clock rates over long cables. The downside is that delay compensation increases system complexity. In systems where delay compensation is not feasible, or in systems with short cables, using transceivers with short propagation delays has significant advantages. Low propagation delay allows for higher clock rates without the need to introduce delay compensation into the system.
Figure 4. Experimental setup
Host implementation
The host implementation includes a serial port and a communication stack. Encoder protocols are not compatible with standard ports (such as UART), thus preventing the use of most peripherals on general-purpose microcontrollers. However, dedicated communication ports can be implemented in hardware using the programmable logic of an FPGA, supporting advanced features such as latency compensation. While the FPGA approach is flexible and can be customized for specific applications, it also has drawbacks. Compared to processors, FPGAs are more expensive, consume more power, and have longer time-to-market.
The EnDat interface discussed in this article is implemented on Analog Devices' ADSP-CM40x, a processor developed for motor control drivers. In addition to peripherals for motor control such as pulse width modulator (PWM) timers, analog-to-digital converters (ADCs), and sinc filters, the ADSP-CM40x also features a highly flexible serial port (SPORT).
These SPORTs can emulate various protocols, including encoder protocols such as EnDat and BiSS. Due to the rich peripherals of the ADSP-CM40x, it can not only perform advanced motor control but also interface with encoders. In other words, there is no need to use an FPGA.
Test settings
The EnDat 2.2 test setup is shown in Figure 4. The EnDat slave is a standard Kollmorgen servo motor (AKM22), and the EnDat encoder (ENC1113) is mounted on the shaft. Three pairs of wires (data, clock, and power) connect the encoder to the transceiver board. The EnDatPHY has two transceivers and a power supply for the encoder. One transceiver is used for the clock, and the other for the data line. The EnDat master is implemented using an ADSP-CM40x combined with standard peripherals and software. Both the transmit and receive ports are implemented using the flexible SPORT mechanism. The EnDat protocol includes frames of varying lengths, but all frames are based on the same sequence, as shown in Figure 5. First, the master sends a command to the slave, then the slave processes the command and performs the necessary calculations. Finally, the slave sends the result back to the master.
Figure 5. EnDat Transmit/Receive Sequence
The transmit clock (TxCLK) is generated by the ADSP-CM40x processor. Due to system latency, data from the encoder is out of phase with the transmit clock before returning to the processor. To compensate for the transmission delay tDELAY, the processor also generates a receive clock (RxCLK), which is delayed by tDELAY compared to the transmit clock. Ensuring the receive clock is in phase with the data received from the machine is an effective way to compensate for the transmission delay.
The clock signal from the processor is continuous, but the EnDat protocol specifies that the clock can only be applied to the encoder during communication. At all other times, the clock line must be held high. For this purpose, the processor generates a clock enable signal CLKEN, which is sent to the ADM3065E data enable pin. Exactly two clock cycles (2T) later, the host begins issuing commands on TxDATA.
The command is 6 bits long, followed by two 0 bits. To control the data direction of the transceiver, the processor sets the Tx/RxEN bit to 1 during transmission. While the slave is ready to respond, the system enters a wait state; the master continues to apply the clock, but the data lines are inactive. When the slave is ready, the data lines are pulled high to receive data, and then a response is immediately sent. After receiving an n-bit response, the master sets the CLKEN signal low to stop the clock. At the same time, the ENCCLK signal goes high. The data stream is half-duplex, and the ENC data graph shows the transmit and receive data streams side-by-side.
Experimental results
Figure 6 shows the test results for the EnDat system. The clock frequency used in the test was 8MHz, and delay compensation was achieved through a phase shift of the received clock. The bottom signal is the command from the EnDat master. The command shown here is "Send Position," which is preceded by two 0s, followed by six 1s, and then two more 0s. This command has a total of 10 bits. The encoder's response is the third signal from the top. The merge data line is the second signal from the top. Finally, the top signal is the clock applied to the encoder.
