A high-speed serial interface transmitter control layer circuit was designed based on the JESD204B standard.

0 Introduction

In fifth-generation mobile communication, high-performance A/D and D/A converters are the core components for its development. Therefore, with the increase in converter resolution and sampling rate, multi-channel parallel data transmission not only increases the pin design of the chip, but also increases the hardware overhead of board-level routing and system interconnection, directly increasing the system cost. Moreover, when the data rate exceeds 1Gb/s, low-voltage differential signaling (LVDS) technology is difficult to meet the bandwidth requirements of the converter. Therefore, high-speed serial interfaces for data converters are becoming a trend to support increasingly stringent requirements such as faster converters, flexible clocks, and deterministic delays [1].

The JESD204B is a serial data interface for high-speed data converters. It not only overcomes the performance degradation caused by parallel data transmission in LVDS, but also supports up to 12.5Gb/s, which is 10 times higher than the throughput of LVDS. It reduces I/O requirements and package size, lowers static power consumption, and saves system costs.

At present, the mainstream high-speed and high-precision data converter chips all adopt the JESD204B interface, such as the 14-bit 2.6GS/s dual-channel analog-to-digital converter AD9689 recently released by ADI and the 12-bit 8GS/s RF analog-to-digital sampling chip ADC12J4000 launched by TI[2]. Although the relevant technologies in China are lagging behind those abroad, universities and research institutions have conducted relevant research for different applications and have made certain progress. This paper designs the control layer circuit of the high-speed serial interface transmitter based on the JESD204B standard, which mainly includes the transmission layer and the data link layer. The correctness of the control layer circuit is verified by the hardware simulation platform built, and its performance is also ideal.

1. Overview of JESD204B Standard

JESD204B is a standard for connecting digital-to-analog converters (DACs) to back-end digital signal processing equipment via a serial interface link. The standard's architecture can be divided into an application layer, transport layer, data link layer, and physical layer, functionally treating the receiver interface as the reverse of the transmitter interface. The application layer is responsible for JESD204B link configuration and data mapping. The transport layer primarily repackages data structures according to the user's data format configuration to map them as 8-bit bytes. The scrambling layer is an optional module that primarily expands the spectrum by scrambling and descrambling 8-bit bytes, thereby reducing electromagnetic interference. The data link layer mainly implements operations such as synchronization character generation, multi-frame synchronization, link alignment, and link synchronization for channel alignment monitoring and maintenance, as well as 8B/10B encoding and decoding. The physical layer supports high-speed serial data transmission and reception, and conversion between serial and parallel processing. Its structure is shown in Figure 1.

2. Design and Implementation of the Transmitter Control Layer Circuit

Based on the requirements of the 3GS/s 12bit high-speed, high-precision A/D converter and the Class 1 operating mode in the JESD204B standard, a complete transmitter control layer circuit framework was constructed, as shown in Figure 2. The circuit designed in this paper mainly includes three modules: a transmission layer module, a data link layer module, and an 8B/10B encoder module. First, based on the number of converters M=4 and the number of samples S=4, the 3GS/s 12bit data from the ADC is sent to the transmission layer. Then, after down-conversion, the data is packaged into a parallel array with L=8 channels by adding control characters and tail characters by reading configuration information sent from the Serial Parallel Interface (SPI). Next, the 32bit data from each channel is sent to the data link layer. Synchronization characters, multi-frame synchronization, link alignment, and synchronization are achieved through Code Group Synchronization (CGS), Initial Lane Alignment Sequence (ILAS) stages, and character replacement. Finally, the data is sent to the 8B/10B encoding module to complete the data transmission of the control layer interface.

2.1 Transport Layer Module Design

The transport layer, for the transmitter control layer interface, is the starting point of the entire circuit module design. It primarily packages the received 3GS/s 12-bit ADC data into an 8-bit parallel array by adding control characters and tail characters. Due to the high data rate from the ADC and considering the highest frequency achievable on the FPGA board, the first stage of the transport layer converts it into four parallel 750MS/s 12-bit ADCs. A multi-phase clock generator downsamples each data stream, generating a 4-phase sampling clock with a 90° phase interval of 187.5MHz. Then, based on the SPI register configuration parameters, appropriate data mapping is performed, converting the multi-bit sample data into a series of scrambled 8-bit bytes. Therefore, the overall circuit structure of the transport layer can be divided into five modules: a downsampling module, a sample buffer module, an SPI register configuration parameter reading module, a mode control module, and a framing module.

The downsampling module samples the data at a 4:1 ratio (S₄), thereby reducing the overall system frequency. The sample buffer module temporarily stores the sample data from the downsampling module in ascending order of frequency, with a buffer size defined as 256 bits. Figure 3 shows the data combination format sent from the downsampling module to the sample buffer module; this combination also facilitates data reading during framing. The SPI register configuration parameter module mainly reads the configuration information sent by SPI and provides framing judgment information to the mode control module based on the 10-bit stored parameter values ​​defined in the configuration register. The mode control module determines the current operating mode based on different combinations of configuration parameters. Table 1 lists the six operating modes proposed according to project requirements and the supported mapping framing parameters. The framing module mainly completes the framing of the sampled data from the sample buffer module according to the framing mode information from the mode control module and the data mapping method of the JESD204B standard. This mapping method helps reduce circuit power consumption, save circuit resources, and reduce circuit area.

2.2 Data Link Layer Design

The data link layer is a crucial component of the entire transmitting end. Within the data link layer, initial frame synchronization, initial channel synchronization, and byte replacement are required to establish a correct transmission channel for data transmitted from the transport layer. Then, the data is encoded using 8B/10B encoding, and special control characters are generated to achieve channel alignment monitoring and maintenance. Simultaneously, the design of this module's circuitry must consider resources such as speed, area, and power consumption. Therefore, the data link layer is divided into a link control module, a CGS module, an ILAS module, a character replacement module, and a multiplexer module.

2.2.1 Link Control Module

The link control module controls the entire data link layer. It is mainly responsible for sending corresponding data and control signals during the link layer initialization process, synchronization maintenance process, and resynchronization process, so that other modules can make adjustments based on its feedback information, thereby completing the process from link initialization to normal data transmission operation, as shown in the jump mechanism in Figure 4.

First, upon completion of the link reset or receipt of a resynchronization request, the link enters the CGS phase, continuously sending the prescribed code group synchronization characters. If the synchronization request signal is found to be canceled, the state machine transitions to the ILAS phase. The ILAS phase completes the transmission of four multi-frame sequences, then sends a corresponding indication signal to the state machine, indicating that the sequence has been completed and requesting a state transition. Upon receiving a valid signal, the control module transitions the state machine to the normal data transmission phase and selects the character replacement module to output data.

2.2.2 CGS Module

The CGS phase is the first step in the link layer's initialization process. It primarily uses Comma codes to detect character boundaries, enabling the receiver to identify character boundaries within the continuous serial data stream.

The specific implementation process is as follows: when the link system experiences a reset or resynchronization, the receiver pulls the SYNC synchronization signal low to 0, thus entering the CGS phase. During the CGS phase, the transmitter sends a series of consecutive /K28.5/ characters (no less than F+9 /K28.5/ bytes, where F is the number of bytes per frame). After receiving at least 4 consecutive /K28.5/ characters and defining the boundaries of the out-of-order bit stream, the receiver releases the synchronization request signal to the transmitter. After detecting the release of the synchronization request, the transmitter stops sending /K28.5/ characters on the rising edge of the next local multi-frame clock and then enters the ILAS phase.

2.2.3 ILAS Module

After the system completes the CGS phase, the transmitter immediately enters the ILAS phase. The ILAS phase serves two purposes: transmitting link configuration data and completing frame and multi-frame initialization synchronization. The ILAS consists of four multi-frames, each beginning with the control character /R/=/K28.0/ and ending with the control character /A/=/K28.3/, with normal data in between. This allows the receiver to align the multi-frames using the /A/ character. Additionally, the second 8-bit byte of the second multi-frame is the control character /Q/=/K28.4/, marking the start of link configuration data transmission, which consists of 14 bytes.

2.2.4 Character Replacement Module

In the JESD204B protocol, byte boundary synchronization and multi-channel alignment are accomplished using code group synchronization and initial channel alignment sequences. After the system completes these two stages, the transport layer directly sends user data to the user data stage of the data link layer in non-scrambling mode. At this point, synchronization character replacement is performed on the data to achieve monitoring, correction, and channel alignment, thereby establishing a correct transmission channel between the sender and receiver and improving transmission accuracy. The DATA character replacement module follows these rules:

(1) When the last byte of the current frame is inconsistent with the last byte of multiple frames, if the last byte of the current frame is the same as the last byte of the previous frame, the sender should replace the last byte of the current frame with the control character /F/=/K28.7/. However, if the last byte of the previous frame is already a special control character, the last byte of the current frame should not replace it, and the original data should be transmitted normally.

(2) If the last byte of the current frame is the same as the last byte of multiple frames, and if the last byte of the current frame is the same as the last byte of the previous frame, the sender should replace the last byte of the current frame with the control character /A/=/K28.3/. Unlike rule 1, even if the previous frame has already been replaced with a special control character, the original data should still be replaced.

2.2.58B/10B encoding module

The 8B/10B encoding and decoding method was first proposed by IBM. While the early lookup table method was relatively simple to implement, it was severely limited in terms of speed, area, and power consumption. To meet the JESD204B protocol interface requirements, this paper implements 8B/10B encoding using a simplified encoding table with polarity information.

For the new 8B/10B encoding, the main goal is to increase the circuit operating frequency by using parallel 3B/4B and 5B/6B encoding while ensuring DC balance and conversion density. It also employs special control characters for error detection. Based on this design, this paper divides the encoding circuit into a K-character encoder module and a D-character encoder module. The K-character encoder module uses a direct encoding method, while the D-character encoder module is divided into 5B/6B encoding and 3B/4B encoding. First, the K-character and D-character encodings are selected and preliminary encoding is performed. Then, the corresponding encodings are corrected, and finally, selective output is performed. The main encoding process is shown in Figure 5.

3. Simulation and Verification

3.1 Verification Method

This paper uses Modelsim 10.1 software to complete the front-end simulation verification of the JESD204B transmitter control layer circuit. The hardware simulation verification platform is built using Vivado 16.1 software and JESD204BPHYIP and ReceiverIP[11] in Zynq-7000 series chip XC7Z045FFG900-2 FPGA. The parallel data output by the control layer is sent to PHYIP, and after a series of operations such as serialization, it is sent to JESD204BReceiverIP. Finally, the hardware simulation verification is realized by using the ILA core to capture the real-time waveform of data transmission and comparing the sent and received data, as shown in Figure 6.

3.2 Verification Results

The circuit, synthesized with correct RTL-level code from the functional simulation, was programmed onto the ZC706 development board using Vivado 16.1, and the real-time waveforms of the signals were captured and analyzed using the ILA core. Figures 7(a) and 7(b) are screenshots of the real-time waveforms of user data transmission after the link is established. After passing through the 32-bit data output from the transport layer, the user data from the link layer, the 8B/10B encoding/decoding, and the 32-bit data output from the JESD204BReceiverIP, a comparison revealed that there were no errors in the transmitted and received data, thus verifying the correctness of the data transmission from the control layer circuit at the transmitting end.

The FPGA resources used by the circuit designed in this paper are shown in Table 2. In addition, the power consumption of the entire transmitter control layer circuit is 0.467W, the setup time slack is 0.235ns, the hold time slack is 0.068ns, and the bit rate after IP serialization reaches 7.5Gb/s.

4. Conclusion

With the continuous improvement of converter resolution and speed, the JESD204B serial interface circuit has become the standard interface for high-speed, high-precision data converters. This paper designs a control layer interface for a 3GS/s 12-bit ADC transmitter based on the JESD204B standard. While meeting the data rate requirements, power consumption and resource optimization are achieved using prescaler technology and polarity information simplification encoding. Hardware simulation verification was completed using a Xilinx Zynq-7000 series chip XC7Z045FFG900-2 FPGA verification system. The serialized bit rate can reach 7.5Gb/s, representing a 50% increase in transmission speed compared to similar interface designs.