Abstract: This paper introduces the design of an intelligent control unit for circuit breakers based on the novel high-performance digital signal processor (DSP) chip TMS320F2812 and the complex programmable logic device (CPLD) MAX7128. The design of the conditioning circuit, F2812 communication module, and CPLD module is described in detail. The embedded real-time multi-tasking operating system μC/OS-Ⅱ is used as the system software platform. The design of the system software and application software (task priority, flow, communication and synchronization, communication protocol, etc.) is discussed, and the program design of the execution circuit is implemented using VHDL. This design scheme can improve the reliability of the intelligent control unit for circuit breakers and facilitate performance expansion. Keywords: Digital signal processor; Complex programmable logic controller; Circuit breaker; Intelligent control With the rapid development of computer technology, signal detection technology, and microelectronics technology, the requirements for circuit breaker control units are constantly increasing. Modern intelligent control units not only require automatic protection, maintenance, and information transmission functions, but also require standard communication protocols to easily form distributed control systems with main control units from different manufacturers. Furthermore, the circuit breaker control unit itself is required to have synchronous closing functionality. This paper introduces an intelligent control unit that uses a digital signal processor (DSP) and an embedded real-time operating system to complete various data processing, communication, and algorithm design. The acquisition of state variables and the output of execution signals are handled by a complex programmable logic device (CPLD). This is primarily based on the reliability of the CPLD's internal hardware circuitry and the real-time performance of state acquisition. This system can meet the requirements of real-time control and reliability. Hardware Design : TMS320F2812DSP Introduction. The TMS320F2812DSP is a 32-bit high-performance digital signal processor from Texas Instruments (TI). It boasts a peak processing speed of 1.5 million instructions per second (MIPS) and can perform 32×32-bit MAC operations in a single cycle. It also features 128k×16 on-chip Flash, 18k×16 on-chip RAM, and numerous on-chip peripherals, including an A/D conversion module, two event managers (EVA and EVB), a CAN bus controller, two serial communication interface modules (SCIA and SCIB), a serial peripheral interface module (SPI), a multi-function serial interface (McBSP), and 56 general-purpose I/O ports. This DSP uses the high-efficiency 32-bit fixed-point CPU TMS320C28xTM as its core processor, and its development can be done using either C28x assembly language or ANSI C/C++ language. In addition, TI provides a virtual floating-point math function library (IQ Math Library), a Fast Fourier Transform (FFT) algorithm function library, a filter library, etc., which can significantly simplify application system development. The powerful functions of the TMS320F2812 enable it to meet the design requirements of an embedded intelligent control unit. System Hardware Design The main tasks of the intelligent control unit include: processing control commands from the main control module, monitoring bus power parameters, temperature acquisition, implementing protection control algorithms, detecting the status of switch quantities, controlling the output of switch quantities, and communicating with the monitoring center. To achieve the above functions and fully utilize the powerful peripheral functions of the TMS320F2812 DSP and the advantages of the embedded operating system, the DSP mainly performs analog signal acquisition, data processing, algorithm implementation, temperature acquisition, communication, and command processing. To ensure rapid status detection and reliable output execution signals, the CPLD will be used for status monitoring, communication with the DSP, status signal output, and control of external high-voltage circuits. The system structure is shown in Figure 1. The system hardware design includes the design of various conditioning circuits, CAN bus communication drivers, RS-232 bus drivers, RS-485 bus drivers, and the internal circuitry of the CPLD. Figure 1: Intelligent Control Unit System Structure Diagram; Conditioning Circuit Design The conditioning circuit includes an AC voltage acquisition conditioning circuit, a switch quantity acquisition conditioning circuit, and a switch quantity control drive circuit. AC voltage signal acquisition uses the F2812's built-in 12-bit A/D conversion module. This module has a sample-and-hold circuit and requires an input voltage range of 0–3V. Therefore, an isolation circuit consisting of a voltage transformer, a current-to-voltage conversion circuit, and an RC filter, and a conditioning circuit consisting of an amplifier, voltage booster, voltage follower, and limiter, are designed to convert a 220V/50Hz voltage signal into a 0–3V voltage signal. Switch quantity acquisition is implemented using a CPLD. Because switching signals frequently exhibit jitter, the conditioning circuit must incorporate measures to eliminate this jitter. The conditioning circuit employs capacitor C to filter out voltage spikes in the input signal (primarily targeting high-frequency interference), a 12V Zener diode to filter out interference signals (primarily targeting low-frequency interference), an optocoupler to prevent external signals from affecting the internal circuitry, and diode VD to protect the LED in the optocoupler from reverse-biased breakdown. The switching control signal is output via the CPLD's I/O pins. The output signal drives external high-voltage devices via the optocoupler TLP127. Since this intelligent control unit primarily controls the closing and closing of circuit breakers, and the closing process generates strong electromagnetic effects, direct driving via the DSP's GPIO pins could cause external electromagnetic interference to malfunction or reset the DSP, severely impacting execution. Therefore, all switching inputs and outputs in the system are handled by the CPLD, enhancing its reliability. The F2812 communication module features an enhanced CAN controller eCAN module, which fully supports the CAN 2.0B protocol. Its performance is significantly improved compared to existing DSP-embedded CAN controllers. During CAN bus communication, data transmission is more flexible and convenient, with larger data volumes, higher reliability, and more complete functionality. Therefore, this design uses the CAN bus to realize communication for the intelligent terminal. The hardware design of the communication module mainly focuses on the design of the CAN bus driver circuit. The Philips PCA82C250 CAN transceiver is selected as the interface between the F2812's CAN controller and the physical bus to achieve differential transmission and reception of the bus. To prevent the introduction of interference signals, a high-speed optocoupler 6N137 is used to isolate the F2812 and the physical bus. The RS-232 driver chip is directly selected from the MAX232 driver chip, while the RS-485 driver chip is the SNLBC184. Furthermore, to prevent interference signals from entering, an optocoupler TLP521 is used to isolate the F2812 from the RS-232 and RS-485 bus driver chips. CPLD Module Design In this intelligent control unit, the CPLD is a crucial component. The CPLD-based status acquisition and output execution system can operate independently, primarily controlling the asynchronous closing and closing of the circuit breaker, accepting various input button operations and status input/output. During synchronous control, the CPLD receives action commands from the DSP, enabling it to execute synchronous closing operations. Simultaneously, when the status changes, the CPLD issues an interrupt signal, which the DSP reads and processes accordingly or transmits to the monitoring center. The CPLD's input signals mainly include asynchronous closing, closing, and reset inputs; circuit breaker position signals; switch trolley position signals; undervoltage trip; overcurrent trip; and system voltage signals. Its information output module primarily displays whether the circuit breaker is ready for operation, its closing/opening status, the circuit breaker's action execution status, and outputs control commands for the circuit breaker's operation. The CPLD control block diagram is shown in Figure 2. As a standalone control and execution mechanism, the CPLD can generate corresponding operating circuits by writing appropriate VHDL code. This includes latching, judging, and processing various input signals, executing various command signals, and controlling output signals. Software Design Software design includes system software design and application software design. Figure 2 shows the control block diagram of the CPLD. The main task of the system software design is to port μC/OS-II to the F2812; the main task of the application software design is to implement the system functions. System Software Design: Introduction to μC/OS-II The system software in this design uses the publicly available source code of the real-time operating system μC/OS-II. It is a priority-based, portable, firmware-enabled, customizable, preemptive real-time operating system, and most of its source code is written in ANSI C. Porting μC/OS-II to the F2812 To use μC/OS-II, the kernel must first be successfully ported to the CPU being used. The porting of μC/OS-II to the F2812 includes four parts: a. Define processor-related constants, macros, and data types in OS_CPU.H. For example, the definitions for disabling and enabling interrupts are #define OS_ENTER_CRITICAL() asm "DINT" and #define OS_EXIT_CRITICAL() asm "EINT", respectively. b. Adjust and modify the header file OS_CFG.H to reduce or modify μC/OS-II system services and decrease resource consumption. For example, #define OS_MBOX_EN0 disables mailbox-related code. c. Write the C language file OS_CPU.C. Since several other functions are not used in this design, this section mainly focuses on writing the function OSTaskStkInit(). OSTaskStkInit() initializes the task's stack structure, making it appear as if an interrupt has just occurred and all registers have been saved to the stack. d. Write the assembly language file OS_CPU.ASM. This document includes four sub-functions: OSStartHighRdy() (runs the highest priority task), OSCtxSw() (task-level task switching), OSIntCtxSw() (interrupt-level task switching), and OSTickISR() (μC/OS-II time tick interrupt function). These are the key and challenging aspects of the μC/OS-II porting process. The proper implementation of these functions is fundamental to ensuring the operation of μC/OS-II. After completing the above steps, μC/OS-II can run. Application Software Design Based on the functional requirements of the intelligent control unit, the system is divided into 11 tasks and 3 interrupts: an AC voltage acquisition module, a data processing module, a circuit breaker action time prediction module, a communication module, and an interface module with the CPLD. Each task is assigned a certain priority, task, and interrupt definition according to its real-time requirements and with reference to the Monotonic Execution Rate (RMS) scheduling method, as shown in Table 1. The highest priority task is the Start task (TaskStart), which is the first task to run after system startup. This task initializes the system and related peripherals, performs necessary self-tests, and then creates the remaining tasks. After creating the remaining tasks, this task deletes itself, freeing up system resources for other tasks, and the entire system begins normal operation. The sample code for this task is as follows: /* System and peripheral initialization */ /* System self-test */ /* Create tasks */ StartCpuTimer2(); /* Start time slice */ OSStatInit(); /* Statistics task initialization */ Create various application tasks for the intelligent control unit; KickDog(); /* WatchDog reset */ OSTaskdel(OS_PRIO_SELF); /* Delete the start task */ Except for TaskStart(), the structure of each task module is an infinite loop. Figure 3 shows a general task flowchart. Figure 3 Task Flowchart Task Communication and Synchronization μC/OS-II provides five methods for data sharing and task communication: semaphores, mailboxes, message queues, event flags, and mutex semaphores. Semaphores can control the right to use shared resources and coordinate the execution of external events and tasks, providing the fastest communication for inter-task communication, synchronization, and mutual exclusion. μC/OS-II provides three types of semaphores: binary, counting, and mutex. Event flags allow tasks to synchronize with multiple events; synchronization with any one of multiple events is called independent synchronization, while synchronization with all events is called associative synchronization. Mailboxes are a communication mechanism that can send a pointer variable that points to a data structure containing a specific message. Message queues are another communication mechanism that allows a task or interrupt service routine to send pointer-defined variables to another task; the data structure pointed to by each pointer varies depending on the specific application. Mutex semaphores are a special type of binary semaphore, primarily used to solve inherent mutual exclusion problems and reduce the need for priority flipping in practical applications. When designing the intelligent control unit software, these communication mechanisms provided by μC/OS-II are fully utilized to coordinate the operation of independent tasks. The F2812 provides the standard CAN 2.0B bus protocol for communication protocol implementation . This protocol is a physical layer protocol. Since this intelligent control unit is used in power system control, common application layer protocols in power systems include CDT, MODBUS, and DNP3.0. In this design, the application layer protocol will be MODBUS. The implementation of the communication protocol is relatively complex, but due to the use of a real-time operating system, the implementation can be uniformly managed by the operating system, mainly completed by data receiving, sending, packing, and unpacking tasks. In summary: a. The design uses the new high-performance DSP TMS320F2812 chip with multiple peripherals, greatly reducing the workload of system hardware design and shortening the development cycle. The design adopts a method of separating the DSP minimum system and conditioning circuit design, and uses a multi-layer board structure and a large number of surface-mount components in the DSP minimum system design to improve system stability and electromagnetic compatibility. b. As an embedded operating system based on priority scheduling, the reasonable allocation of task priorities is crucial for the normal operation of the system. In this design, the allocation of task priorities first considers meeting the system's real-time requirements, and then, under the same conditions, considers the execution frequency of the tasks. Through repeated adjustments, the priority allocation table 1 is finally determined. c. This project utilizes a CPLD-based execution circuit design. Due to the reliability and fast response of the CPLD's internal hardware structure, it is very suitable for power system control; therefore, using a full CPLD (or ACTELFPGA) should be a research direction. d. As a new member of TI's 2000 series, the F2812 is currently in the exploratory stage of development and design in China. The system design concept based on TMS320F2812+μC/OS-Ⅱ proposed in this paper will play a certain role in promoting the learning and use of the F2812.