Introduction Microcomputer protection devices refer to digital relay protection devices composed of microcomputer systems. In China's underground coal mine high-voltage (6kV) power supply systems, the vast majority operate under transformer neutral point insulation (three-phase three-wire system), transmitting power through power cables. The underground coal mine environment is harsh and confined, with power cables constantly exposed to moisture, water, and corrosion, resulting in poor heat dissipation and easily deteriorating insulation performance, frequently leading to single-phase leakage or single-phase grounding faults. These faults cause an increase in the voltage of the normal phase; if power is not cut off in time, it can cause multi-phase short circuits, forcing power outages and further escalating the power fault. High-voltage explosion-proof switch microcomputer protection devices are installed in high-voltage explosion-proof switches to provide comprehensive protection against single-phase leakage or single-phase grounding, short circuits, overcurrent, insulation monitoring, over/undervoltage, and other faults in underground cables and electrical equipment. They can quickly disconnect faulty circuits, prevent the accident from escalating, and notify maintenance personnel to promptly investigate and eliminate the fault source. Therefore, high reliability requirements are placed on high-voltage explosion-proof switch microcomputer protection devices: they must operate quickly when a fault occurs and must not operate erroneously when no fault occurs. However, when high-voltage switches switch on and off inductive loads (mainly inductive loads such as motors in underground electrical equipment), arcing of the switch contacts generates strong electromagnetic interference and surge interference, which can severely cause CPU program crashes. This electromagnetic interference is the number one strong interference source for high-voltage explosion-proof switch microcomputer protection systems, mainly intruding into the microcomputer protection system through power lines and AC transformer entry channels. Since the microcomputer protection system operates under this strong electromagnetic interference for extended periods, its anti-interference performance has become one of the important indicators for evaluating such systems. The fundamental way to improve the anti-interference performance of microcomputer protection devices is to block the coupling channels of common-mode interference, improve the anti-interference capability of sensitive circuits, and rationally design grounding and discharge circuits. Electromagnetic compatibility (EMC) design is a complex systems engineering project. Considering anti-interference design from a hardware perspective is essential, but completely eliminating interference from a hardware perspective is impossible. Software considerations such as digital filtering are also necessary, making perfection difficult to achieve. Domestic researchers have conducted extensive research on anti-interference technologies in single-chip microcomputer systems and microcomputer measurement and control systems, publishing numerous papers on anti-interference techniques, which can be divided into two main categories. One type is to block the intrusion channel of interference signals from the hardware circuit, such as adding a pre-filter to the analog channel, adding a power filter to the power input, adding optocoupler isolation to the switch input and output, anti-interference technology of pCB layout and wiring, grounding technology, shielding technology, etc.; the other type is software anti-interference measures, including digital filtering, instruction redundancy, software traps, hardware and software watchdogs, etc. Hardware anti-interference measures are to keep interference signals out of the door, which is the main direction of electromagnetic compatibility design. Software anti-interference is to use the flexibility of software design to offset the influence of interference before the hardware fails, and can only play an auxiliary anti-interference role. There is very little literature on the reliability design of the control output of microcomputer protection devices. In summary, there are two common measures to prevent the control output from going out of control: hardware redundancy design and software redundancy design. The basic method of hardware redundancy design is to adopt a dual or multi-CPU structure, one CPU is responsible for the start of protection, and the other CPU is responsible for the execution of protection. The two CPUs are ANDed to start the control output. Software redundancy design mainly adopts the following measures: (1) Set multiple trip commands, execute the tripping in multiple control instructions, execute a verification program between each instruction, and set the corresponding flag bits. The CPU executes the next instruction only after verifying that the flag bit matches; otherwise, it initializes again. (2) Set the status information of the current output status register. The system runs a self-test program to check and test these statuses in a loop. If interference errors are found, the error information of the output channel is corrected in time. Multi-CPU structure design is an effective measure to prevent protection malfunctions and improve the reliability of microcomputer protection systems. However, the use of multi-CPU structure makes the hardware structure complex, debugging cumbersome, and costly. Moreover, when multiple CPUs run programs simultaneously, the control output will also be out of control, which may cause malfunctions. Software redundancy design is proposed under the condition that the program runs normally (i.e., assuming that the CPU runs the program correctly and does not go astray). If the program runs out of control and the software redundancy design program cannot be executed, the control output will be out of control. Even if the watchdog circuit works and the CPU is reset to return to the normal program, the shortest time will be several milliseconds. During this period, interference signals are enough to cause the control output to trip malfunctions. Obviously, the above two methods cannot completely ensure the reliability and safety of the relay protection control output. For microprocessor-based protection systems, the most crucial aspect is preventing malfunctions in relay protection control outputs when strong interference causes the program to malfunction. In developing a microprocessor-based high-voltage explosion-proof switch protection system配套的大高爆防转微计算机保护系统 for the KJ118 mining substation remote monitoring system, this paper creatively proposes using CPLD technology to enhance the reliability of the microprocessor-based protection control outputs, addressing the characteristics of these outputs. A CPLD-based anti-interference microprocessor-based protection control output hardware circuit was successfully designed. This novel method of anti-interference design based on the CPLD control interface, described in this paper, is simpler, more economical, and more reliable than a multi-CPU structure. It does not rely on the CPU's inherent anti-interference performance; even if the CPU program malfunctions, the control interface still maintains high anti-interference performance and will not generate false tripping levels, thus completely solving the reliability problem of relay protection system control outputs. The advantages of CPLD technology in microprocessor-based protection devices: CPLD (complex programmable logic device) and FPGA (field programmable gate array) are two major programmable ASIC (application-specific integrated circuit) chips, both of which can be described and programmed using VHDL (very high-speed integrated circuit hardware description language). CPLD gate arrays are smaller than FPGAs. CPLDs are primarily based on product terms, making them easier to implement complex combinational logic. CPLDs have fewer logic macrocells than FPGAs, making FPGAs more suitable for handling a greater number of flip-flop sequential logic. FPGAs are primarily based on SRAM lookup tables. While FPGAs offer flexible circuit configuration, their latency is unpredictable, resulting in a higher actual transmission latency than CPLDs. CPLDs use EEPROM programming technology, ensuring that configuration information is not lost when power is lost. FPGAs utilize SRAM switching technology, allowing for online reconfiguration upon power-up. Theoretically, this allows for unlimited configuration and true online configurability. However, configuration information is lost upon power-down, necessitating reconfiguration via serial EEPROM or a microcontroller. For applications with a relatively small number of I/O pins and flip-flops, CPLDs offer superior ease of use and programming security compared to FPGAs. The digital combinational logic and sequential logic circuits in microprocessor-based protection systems are generally small in scale, making CPLD chips suitable for miniaturization and intelligent design. Microprocessor-based Protection Device Control Interface Design The control interface of a microprocessor-based protection system consists of I/O interfaces and miniature relays. A typical circuit divides the closing and opening relays into two levels, with the first level controlling the second. The second level controls the closing and opening contactors in the main circuit. The block diagram is shown in Figure 1. The two-level relays effectively isolate interference generated by the switching of the main circuit's closing and opening contactors. The closing command execution sequence is: OUT1→OUT2→OUT4. The execution sequence of the tripping command is: OUT1→OUT3→OUT4. If the I/O interface is directly controlled by the CPU, when the CPU is interfered with and the program runs away or the CPU chip malfunctions, causing the I/O interface to become uncontrollable, and happens to generate the level required for tripping or closing, the relay protection control output will inevitably malfunction. Figure 1 shows the principle of the relay protection control output. Therefore, the interlocking and redundancy design of the relay protection control output is the key to preventing malfunctions. Strictly monitoring the execution sequence of multiple tripping and closing commands and not allowing disordered tripping and closing commands to pass is the fundamental measure to prevent malfunctions of the control output. The orderly execution of multiple tripping and closing commands can be regarded as a state change sequence. By monitoring this state sequence with a CPLD state machine, the passage of disordered states can be prevented, achieving interference-free control of the control output. Design of Anti-interference Control Interface Based on CPLD State Machine When designing a DSP-based microcomputer integrated protection system for a high-voltage switchgear, a CPLD chip is used to implement the I/O interface shown in Figure 1. A finite state machine is designed to monitor the state inputs I1, I2, and I3. The state machine output serves as the enable and disable signals for the overall opening and closing commands. The CPLD-based microcomputer protection control interface is shown in Figure 2. Figure 2: State Encoding of Multiple Opening and Closing Commands for CPLD Control Interface of Microcomputer Protection The state machine has 3-bit binary inputs, resulting in 2³ = 8 states. A binary encoding method is used to list the initial state S0 of the control interface to all possible state transitions in an encoding table, as shown in Table 1. The state encoding table is the basis for writing VHDL programs. Table 1: State Machine Encoding Table for Microcomputer Protection Control Interface The clock frequency of the state machine is 5MHz. The reset signal /Reset comes from the system reset signal of the DSP microcomputer protection device and initializes the state machine. State machines can be designed using single-process, dual-process, or three-process programming. Based on the application characteristics of microcomputer protection and control interfaces, a dual-process approach is recommended, consisting of a sequential process and a combinational process. The sequential process is responsible for the transition from the previous state to the current state and asynchronous reset. The combinational process determines the state machine output based on the current state and the new next state based on the state input. The logic diagram of the dual-process state machine is shown in Figure 3. Figure 3: Logic Diagram of a Dual-Process State Machine. The behavior and code of a state machine are flow control codes, easily implemented using CASE and IF statements in VHDL. The sequential process and the combinational process communicate synchronously using current and next state signals. State Machine Simulation Waveforms The state machine designed in VHDL was simulated using Altera's EDA tool MAX+plus. The simulation waveforms are shown in Figure 4. Figure 4. State Machine Simulation Waveform: Analysis of CPLD State Machine Anti-interference Control Principle CPU-based microcomputer systems execute machine instructions sequentially according to the instruction cycle. Once interfered with, the program deviates from its intended path, causing the CPU to crash. A common countermeasure is to set a watchdog timer to reset the CPU hardware, allowing it to resume normal operation. However, the time from CPU crash to watchdog reset typically takes several milliseconds to 1-2 seconds. During this uncontrolled period, the state of the relay protection control output is unpredictable, potentially posing a threat to the relay protection system, and in severe cases, causing malfunctions. In contrast, a CPLD-based state machine system has a state transition cycle of only one clock cycle. If the clock frequency is 5MHz, the clock cycle is 0.12Ls. If the state machine is interfered with and enters an illegal state before transitioning to a legal state, it only takes two clock cycles, or several hundred nanoseconds, which is insufficient to harm the system's operation. Therefore, using a CPLD state machine to control the microcomputer relay protection control interface can achieve interference-free control and obtain highly reliable control for the relay protection system. In comparing the reliability of DSP chips and CPLD chips, DSPs have numerous peripheral interfaces, including both analog and digital input signals, and both analog and digital voltages. CPLDs, on the other hand, only have digital interfaces and a single voltage input, making them much less susceptible to damage from external interference. Furthermore, the CPLD state machine contains multiple processes, essentially possessing a "multi-CPU" function with parallel computation. For unqualified inputs, the decision state machine outputs 0. Therefore, the author believes that the hardware redundancy design of dual-CPU control is far less reliable than the control interface of the CPLD state machine. Conclusion The relay protection control interface was implemented using Altera's MAX7000 series EMP7128SLC84-15, directly connected to the TMS320F240 DSP chip bus. When the DSP executes multiple closing or opening commands, no waiting cycle is required; only three consecutive closing or opening commands need to be executed, and the CPLD state machine can immediately decide whether to allow the overall command to proceed. Experiments show that the relay protection control interface implemented using CPLD has the characteristics of high speed, small hardware size, simple interface, and high reliability. This interface was applied to a digital integrated protection device for high-voltage switchgear based on TMS320F240. It was put into operation in October 2003 at the Qishan Coal Mine underground mining area substation of Xuzhou Mining Bureau, along with the KJ118 type mine substation remote monitoring system, for industrial testing. It has been operating normally for over six months. On-site manual operation of the high-explosive switch, remote control command operation of the ground host, and fault protection tripping tests at the mining area substation showed that there had never been any instances of CPU program malfunction due to strong electromagnetic interference such as high-voltage switch operation, demonstrating very high reliability. This paper uses a novel CPLD state machine method to study the control reliability of microcomputer protection systems, which has strong filtering capabilities for transient interference signals. Although some software measures to prevent microcomputer protection system program malfunctions have some effect, they cannot truly solve the problem of control port loss of control during program malfunctions. The CPLD state machine control interface proposed in this paper truly solves this problem and can be extended to the design of anti-interference control interfaces for various microcomputer control systems.