Since this design is parameterizable, meaning that an encoder with a corresponding data bit width can be implemented by setting the input data bit width, let's assume the encoder's input data bit width is A and the output data bit width is B. From our knowledge of digital electronics, we know the relationship is B = log2(A), where log2(x) is a logarithmic function to base 2. Verilog HDL has a corresponding system function: $clog2(x).
The encoder can be implemented in two ways: first, by traversing the data bits; and second, by deriving the formula.
<1> There are two methods for iterating through the data bits, both implemented using a for loop. The first method iterates from the least significant bit to the most significant bit of the input data and checks if the encountered bit is 1. If it is 1, the corresponding binary code is the encoder's output. The second method iterates from the most significant bit to the least significant bit of the input data and checks if the encountered bit is 1. If it is 1, the corresponding binary code is the encoder's output.
<2> By deriving the formula. Below is the input-output correspondence of the 8-3 encoder:
To summarize the above formula, a certain bit of the encoder output can be determined by the result of the OR operation of the input bits that may cause that bit to be 1. For example, performing an OR operation on the bits with the 0th bit of all binary index numbers in the encoder input din that are 1 will result in the encoder output bit 0 dout[0]; performing an OR operation on the bits with the 1st bit of all binary index numbers in the encoder input din that are 1 will result in the encoder output bit 1 dout[1]; and so on.
The design utilizes two for loops: one for loop counts the index numbers input to the encoder, and the other for loop counts the index numbers output by the encoder. It also checks the corresponding bits of the input binary index number to perform the appropriate OR operation.
