I. Background of Changes in Embedded System Design Methodologies
The evolution of embedded system design methodologies is generally driven by application requirements and the advancement of IT technologies.
With the continuous innovation and development of microelectronics technology, the integration level and process technology of large-scale integrated circuits are constantly improving. The combination of silicon materials and human ingenuity has enabled the production of large quantities of low-cost, high-reliability, and high-precision microelectronic structural modules, driving the development of a completely new technological field and industry. Based on this, the concept of programmable devices and microprocessor technology have been developed, allowing software to modify and implement the functions of hardware. The widespread application of microprocessors and various programmable large-scale integrated circuits and semi-custom devices has opened up a new world of applications, profoundly influencing and gradually changing human social activities such as production, life, and learning.
The significant improvement in the performance of computer hardware platforms has enabled the implementation of many complex algorithms and user-friendly interfaces, greatly improving work efficiency and providing a physical basis for the computer-aided design of complex embedded systems.
High-performance EDA synthesis development tools (platforms) have made great strides, and their level of automation and intelligence has been continuously improved. They provide easy-to-learn and convenient development integration environments for complex embedded system design, integrating editing, placement, routing, compilation, synthesis, simulation, testing, verification and device programming for different purposes and levels.
The development of Hardware Description Languages (HDLs) has provided a working medium for building various hardware models in the design of complex electronic systems. Their strong descriptive and abstractive capabilities have brought about significant changes to hardware circuits, especially semi-custom large-scale integrated circuit design. Currently, commonly used HDLs include VHDL (IEEE STD1076 standard), Verilog HDL (IEEE STD1364 standard), and Altera's AHDL (company standard).
Due to the development and standardization of HDL (HDL for Integrated Circuits), a number of companies worldwide have emerged that specialize in designing various integrated circuit functional modules using HDL. Their task is to describe the function and structure of integrated circuits using HDL according to common or special functions, and to form different levels of IP core modules through different levels of verification, for chip designers to assemble or integrate.
An IP (Intellectual Property) core module is a pre-designed, or even verified, integrated circuit, device, or component with a specific function. It comes in several different forms. IP core modules have three levels of design: behavioral, structural, and physical. These correspond to three layers: "soft IP core," which primarily describes the functional behavior; "firm IP core," which completes the structural description; and "hard IP core," which is based on the physical description and has been verified through process technology. This is equivalent to the design technology of integrated circuits (devices or components) blanks, semi-finished products, and finished products.
Soft IP cores are typically submitted to users using HDL text. They have undergone behavioral-level design optimization and functional verification, but contain no specific physical information. Based on this, users can synthesize the correct gate-level netlist and perform subsequent structural design, offering maximum flexibility. They can be easily integrated with other external logic circuits using EDA synthesis tools, and designed into devices with different performance characteristics according to various semiconductor processes. Commercially available soft IP cores generally have a total gate count of over 5000. However, improper subsequent design can lead to the failure of the entire result. Soft IP cores are also known as virtual devices.
Hard IP cores are physical designs based on a specific semiconductor process. They have a fixed topology and specific process, and have been verified to guarantee performance. They are provided to users as a circuit physical structure mask layout and a complete set of process documents, offering a ready-to-use, complete technology.
The design depth of a solid IP kernel falls between that of a software IP kernel and a hardware IP kernel. In addition to completing all the design aspects of a hardware IP kernel, it also performs gate-level synthesis and timing simulation. It is typically submitted to users in the form of a gate-level netlist.
Manufacturers such as TI, Philips, and Atmel have developed their own unique microcontrollers that are compatible with Intel MCS51 by licensing Intel's MCS51 IP core modules and combining them with their own strengths.
Commonly used IP core modules include various CPUs (32/64-bit CISC/RISC CPUs or 8/16-bit microcontrollers/microcontrollers, such as the 8051), 32/64-bit DSPs (such as the 320C30), DRAM, SRAM, EEPROM, Flash memory, A/D, D/A converters, MPEG/JPEG, USB, PCI, standard interfaces, network units, compilers, encoders/decoders, and analog device modules. This rich library of IP core modules provides a fundamental guarantee for rapidly designing application-specific integrated circuits and single-chip systems, and for quickly capturing market share.
Advances in software technology, particularly the introduction of the Embedded Operation System (EOS), have provided underlying support and a highly efficient development platform for developing complex embedded system application software. EOS is a powerful and widely used real-time multitasking system software. It generally possesses all the system resource management functions found in operating systems, and users can implement various resource management functions through application programming interfaces (APIs). User programs can be developed and run on top of EOS. Compared to general-purpose operating systems, it features a smaller, more efficient kernel, lower overhead, stronger real-time performance, and higher reliability. A comprehensive EOS also provides drivers for various devices. To adapt to network and Internet applications, it can also provide TCP/IP protocol support. Currently popular EOS systems include 3Com's PalmOS, Microsoft's Windows CE and Windows NT Embedded 4.0, the University of Tokyo's Tron, various open-source embedded Linux distributions, and domestically developed technologies such as HopenOS from the Kaisheng Group and HBOS from Zhejiang University.
II. Changes in Embedded System Design Methods
In the past, programmers who were good at software design generally kept their distance from hardware circuit design, as hardware design and software design were considered to be completely different technologies.
With the development of electronic information technology, designers with an electronic engineering background often gradually dabble in software programming. This primarily involves learning assembly language programming through the application of microcontrollers (commonly known as single-chip microcomputers in China). When designing larger-scale distributed control systems, the ubiquitous PC is inevitably used as the upper-level machine, allowing for further learning of high-level languages such as QuickBASIC, C, C++, VC, and VB to program system programs, design system interfaces, and establish a centralized distributed control system through multi-machine communication with the front-end machine controlled by the single-chip microcomputer.
Designers with a software programming background rarely have an interest in learning application circuit design. However, with the rapid development of computer technology, especially the invention of Hardware Description Language (HDL), system hardware design methods have changed. The hardware components and behavior of digital systems can be fully described and simulated using HDL. In this context, designing hardware circuits is no longer the sole domain of hardware design engineers. Designers skilled in software programming can use HDL tools to describe the behavior, function, structure, data flow, signal connections, and timing relationships of hardware circuits, designing hardware systems that meet various requirements.
EDA tools allow for two design input methods, catering to the needs of hardware circuit designers and software programmers with different backgrounds. Hardware-oriented designers can use their familiar schematic input method, while software-oriented designers can use a Hardware Description Language (HDL). Because HDL descriptions are used, they more closely resemble system behavior descriptions and are easier to synthesize, transfer in the time domain, and modify. They also allow for the creation of process-independent design documents. Therefore, those skilled in software programming, once they master HDL and some necessary hardware knowledge, can often design better hardware circuits and systems than engineers accustomed to traditional design methods. Thus, engineers accustomed to traditional design should learn to use HDL for description and programming.
III. Three Levels of Embedded System Design
Embedded system design has three different levels:
1. Level 1: Design method using PCBCAD software and ICE as the main tools.
This is the method that Chinese microcontroller application system designers have been using in the past and continues to use today. The steps are to first abstract and then to concretize.
Abstract design mainly involves refining the system functions based on the functional requirements of the embedded application system, dividing them into several functional modules, drawing a system functional block diagram, and then allocating hardware and software functional implementations to the functional modules.
The specific design includes hardware and software design. Hardware design mainly involves selecting and combining the components required for each functional module based on performance parameter requirements. The basic principle for selection is to choose the most cost-effective general-purpose components available on the market. When necessary, it is necessary to conduct separate tests, functional verification, and performance testing on each uncertain part to find a relatively optimized solution from module to system and draw the circuit schematic. A key step in hardware design is to use computer-aided design (CAD) software for printed circuit board (PCB) to lay out and route the system components, followed by PCB fabrication, assembly, and hardware debugging.
The most labor-intensive part is software design. Software design permeates the entire system design process and mainly includes task analysis, resource allocation, module division, process design and refinement, coding and debugging, etc. The majority of the workload in software design is concentrated on program debugging, making software debugging tools crucial. The most commonly used and effective tool is an online emulator (ICE).
2. Level 2: Design method using EDA tools and EOS as development platforms.
With the development of microelectronics technology, various general-purpose programmable semi-custom logic devices have emerged. In hardware design, designers can utilize these semi-custom devices to gradually integrate several standard logic devices that would otherwise require interconnection via printed circuit board (PCB) traces into application-specific integrated circuits (ASICs). This transforms the complexity of PCB layout and routing into the complexity of configuration within the semi-custom device. However, designing semi-custom devices does not require designers to have knowledge and experience in semiconductor processes and on-chip integrated circuit layout and routing. As semi-custom devices become larger and more integrated, the costs of interconnecting devices on the PCB decrease, along with assembly and debugging costs. This not only significantly reduces PCB area and the number of connectors, lowering overall system costs and increasing the flexibility of programmable applications, but more importantly, it reduces system power consumption, increases system operating speed, and greatly improves system reliability and security.
In this way, hardware designers have gradually shifted from selecting and using standard general-purpose integrated circuit devices to designing and manufacturing some special-purpose integrated circuit devices themselves, and these technologies are supported by various EDA tool software.
Semi-custom logic devices have evolved through the stages of programmable logic arrays (PLAs), programmable array logic (PALs), general-purpose array logic (GALs), complex programmable logic devices (CPLDs), and field-programmable gate arrays (FPGAs). The trend is towards increasing integration and speed, enhanced functionality, more rational structures, and greater flexibility and ease of use.
Designers can use various EDA tools and standard CPLDs and FPGAs to design and manufacture user-specific large-scale integrated circuits. Then, through a bottom-up design approach, they can lay out and route the self-designed integrated circuits, programmable peripheral devices, selected ASICs, and embedded microprocessors or microcontrollers on a printed circuit board to form a system.
3. Level 3: Design method based on IP kernel library and using hardware and software co-design technology.
Since the 1990s, there has been a shift from "integrated circuit" level design to "integrated system" level design. Currently, we have entered the System-on-Chip (SoC) design stage and are beginning to see practical applications. This design approach does not simply re-integrate all the integrated circuits needed for the system onto a single chip. If this were done, it would be impossible to achieve the high density, high speed, high performance, small size, low voltage, and low power consumption requirements of a single-chip system, especially the low power consumption requirement. Single-chip system design starts from the overall system performance requirements, tightly integrating the design of the microprocessor, model algorithms, chip structure, peripheral devices, and even the devices themselves. Through the co-design of system software and hardware based on entirely new concepts, the entire system's functionality is completed on a single chip. Sometimes, the system may be implemented on several chips. This is because not all systems can be implemented on a single chip; and the manufacturing cost of implementing a certain single-chip system may be too high, rendering it commercially unviable. Currently, the single-chip systems that have entered practical application are still relatively simple, such as smart IC cards. However, several well-known semiconductor manufacturers are working intensively to research and develop complex single-chip systems like single-chip PCs.
Designing a single-chip system from scratch is neither realistic nor necessary. Besides the immaturity and lack of time-tested design leading to unreliable system performance and quality, the excessively long design cycle also diminishes its commercial value.
To accelerate the design cycle and improve system reliability of a single-chip system, the most effective approach is currently to license mature and optimized IP core modules for design integration and secondary development. These IP core modules are then embedded into the SOC using Glue Logic Technology (GLT). IP core modules are the foundation of single-chip system design, and the choice of which level of IP core module to purchase depends on a trade-off between existing resources, time constraints, budget, and other factors. Purchasing hard IP core modules carries the lowest risk but also the highest cost. However, generally speaking, purchasing IP core modules not only reduces development risk but also saves on development costs, as the cost of purchasing IP core modules is typically lower than the cost of designing and verifying them independently. Of course, not all necessary IP core modules are readily available on the market. To maintain market dominance, some companies are unwilling to license (at least temporarily) their key IP core modules. In such cases, it is necessary to develop such IP core modules in-house.
Each of these three levels has its own scope of application. From an application development perspective, the first two methods will be used for a considerable period. The third-level design method is only suitable for designing simple single-chip systems for general application users. Complex single-chip systems can only be designed and implemented by certain large semiconductor manufacturers, and single-chip systems implemented using this method are only worth investing in for widely used, large-scale applications. Some application systems are not suitable for single-chip implementation due to technical or commercial considerations. Once these are commercially available as single-chip systems, users only need to know how to choose them. Therefore, the three levels of design methods will coexist, and the latter will not simply replace the former. Junior application designers will primarily use the first method; experienced designers will primarily use the second method; and highly specialized designers will use the third method for designing and applying simple single-chip systems. However, all designers can utilize the specialized single-chip systems designed using the third method offered by major semiconductor manufacturers.
