Summary The goal of this project is to design an efficient power supply system with digitally adjustable output voltage (VOUT). To ensure output voltage accuracy, a digital closed-loop control is employed to correct for the effects of offset, drift, and load variations (up to 600mA). The circuit includes an output-adjustable buck controller, an ADC and DAC, a voltage reference, and a microcontroller (MCU). In most DC-DC converters, a resistor network located on the FB pin adjusts the converter's output voltage (see Figure 1). In this circuit, the DAC output voltage (VDAC) is used to change the reference voltage of the resistor network, thereby adjusting the converter output (VOUT). The ADC detects the output voltage and sends the result to the microprocessor. The microprocessor adjusts the DAC output to control the system output voltage to a predetermined value. To keep the circuit as simple as possible, the preset output voltage is sent to the microprocessor via the PC's serial communication port (RS-232). This system is very useful in embedded systems that require precise control of the supply voltage. For example, power supplies for ASICs, DSPs, or MCUs, where the supply voltage corresponds to the processor's operating speed. Adjusting the supply voltage to the minimum voltage corresponding to the operating speed can reduce processor power consumption. Required Components and Development Tools The system's main power supply is the MAX1692, a low quiescent current, adjustable output voltage regulator from 1.25V to 5.5V, capable of providing a maximum current of 600mA. The MAX1692 evaluation board provides a validated circuit layout and recommended input, output, and inductor values. The bias of the MAX1692 feedback pin resistor network is provided by a low-power, 12-bit DAC, the MAX5302, which can provide 2.5mA of load drive. The DAC reference voltage is 2.5V. The voltage regulator output voltage is read by a low-power, 12-bit ADC (MAX1286), which automatically shuts off to reduce power consumption between conversions. The ADC reference is provided by a high-precision 5V voltage reference, the MAX6126. Both the ADC and DAC communicate via SPI. The high-precision voltage reference includes output sense and ground sense pins, which are connected to the ADC's reference and ground pins. This ensures the ADC has the highest accuracy reference voltage. [IMG=Fig. 1]/uploadpic/THESIS/2007/12/20071207130723481369.jpg[/IMG] 740）this.width=740" border=undefined> Fig. 1 Buck converter adjusting VOUT to enable FB pin Fig. 1 Buck converter adjusting VOUT to enable FB pin Microprocessor selection The high-speed 8051-compatible microprocessor DS89C420 uses a 32MHz crystal. The vast majority of instructions of this microprocessor are single-instruction cycles and can run at 32 MIPS. The processor can be programmed in-system via J1 port (see Fig. 3). The DS89C420/430/440/450 series user manuals describe how to download firmware via the PC serial communication port using Microsoft HyperTermina. The processor firmware is written in C and can be compiled using the free Sourceforge Small Devices C Compiler (SDCC). [IMG=Fig. 2]/uploadpic/THESIS/2007/12/2007120713073293279S.jpg[/IMG] 740）this.width=740" border=undefined> Fig. 2 The analog section of the power supply system generates a high-accuracy output voltage adjustable from 1.25V to 5V, with a load capacity of up to 600mA. [IMG=Fig. 4]/uploadpic/THESIS/2007/12/2007120713075035683T.jpg[/IMG] 740）this.width=740" border=undefined> Fig. 3 The digital section of the power supply system requires a stable 5V power supply (shared with the analog section). The digital section communicates with the DAC and ADC through a bit-by-bit controlled SPI interface. The serial transceiver (U8) receives the VOUT setting value from the PC, and J1 provides in-system programming for the MCU. Analog Circuit Design To calculate R1, R2, and R3 in the resistor network (see Figure 2), we first assume that the current flowing into the FB pin (IFB) is negligible (the maximum value given in the MAX1692 specification sheet is 50nA), and set R2 to 49.9kΩ. The voltage at the FB pin is 1.25V, and the current I2 is 25mA, which is much higher than 50nA, proving that the decision to ignore IFB is correct. Finally, we calculate R1 and R2: (1) When the DAC output voltage (VDAC) is at its maximum value of 2.5V, the output of the buck regulator (VOUT) should be at its minimum value of 1.25V. Substituting into Equation 1: The first term is zero, so R3 is 50 kΩ. When VDAC is at its minimum value of 0V, VOUT should be at its maximum value of 5V. Substituting into Equation 1: We get R1 to be 75kΩ. The ADC acquires VOUT and transmits it to the MCU via the SPI interface, forming a closed-loop digital control. In the digital circuit design, the DAC and ADC communicate with the MCU via a bit-by-bit controlled SPI bus. The MCU is the master device, while the DAC and ADC are slave devices. The MCU's five pins are designated as SCLK, MOSI, MISO, CSADC (ADC chip select), and CSDAC (DAC chip select). Devices on the bus share SCLK, and a 32MHz crystal is used to supply the MCU's system clock for maximum communication speed. The MCU receives the VOUT value via the PC serial port. The MAX3311 is an RS-232 transceiver that converts RS-232 levels to TTL/CMOS levels. Layout considerations Connect all passive components (bypass capacitors, compensation capacitors, input capacitors, output capacitors, and inductors) to the buck converter using wide leads. The resistor network for these components and the FB pin should be as close to the buck converter as possible to reduce PCB lead resistance and noise interference. A large copper area is required at the buck converter to reduce the IC's operating temperature under heavy loads. Refer to the MAX1692 evaluation board. To maintain signal integrity, analog and digital signal lines must be isolated as much as possible. Place the DAC and ADC close to the buck converter, connecting all analog signals with short leads. Connect digital signals to the MCU in the opposite direction. Place the voltage reference as close to the ADC as possible, and connect the voltage feedback line providing the voltage reference to the ADC's REF and GND pins with short, isolated leads to ensure ADC conversion accuracy. Ensure there are no high-speed signal lines below the MCU. Simultaneously, place the 32MHz clock crystal as close as possible to the MCU's input pins. As with all PCB routing, 90° lead bends are not allowed. Bypass all IC power supplies with 0.1μF ceramic capacitors and mount them as close as possible to the power supply pins. Software The MCU software of this system obtains the VOUT value to be set through the PC serial port, which corresponds to the output voltage of the buck converter obtained by the ADC sampling. Since the MCU has an 8-bit bus and the ADC has a 12-bit resolution, the byte is shifted left by 4 bits (equivalent to multiplying by 16), and the least significant bit of the 4 bits is set to zero. The software is written in C and can be downloaded from the Maxim website. [IMG=Figure 4]/uploadpic/THESIS/2007/12/2007120713080793060Y.jpg[/IMG]740）this.width=740" border=undefined> Figure 4 shows the waveforms of the buck converter output voltage (VOUT) and the DAC output voltage (VDAC) when the load current is 1mA. Figure a shows the VOUT and VDAC waveforms when VOUT changes from 4.5V to 1.5V; Figure b shows the VOUT and VDAC waveforms when VOUT changes from 1.5V to 4.5V. [IMG=Figure 5]/uploadpic/THESIS/2007/12/2007120713081883573R.jpg[/IMG] 740）this.width=740" border=undefined> Figure 5. The waveforms show the output voltage (VOUT) of the buck converter and the output voltage (VDAC) of the DAC when the load current is 350mA. Figure a shows the VOUT and VDAC waveforms when VOUT changes from 4.5V to 1.5V; Figure b shows the test results of the VOUT and VDAC waveforms when VOUT changes from 1.5V to 4.5V. Even under full load, the system can correctly control the converter's output voltage to 1% of the set voltage. Within the error range. Feedback from the ADC can compensate for load variations, offset, and output voltage drift to accurately control the output voltage. Figures 4a and 4b show the performance of the supply voltage with a 1mA load. Figure 5a shows the changes in VOUT and VDAC when VOUT changes from 4.5V to 1.5V, and Figure 5b shows the changes in VOUT and VDAC when VOUT changes from 1.5V to 4.5V. It can be seen that the rate of decrease of VOUT is much slower than the rate of increase. This is due to the discharge of the large output capacitor (see C16 in Figure 2). The converter can charge the capacitor very quickly, but the load cannot discharge it quickly enough. Note that the rates of voltage change are very close because a 350mA load can discharge the capacitor quickly enough. Thus, a sufficiently large load can cause VOUT to increase or decrease at the same rate. Although the voltage can be accurately controlled, the test results also highlight some problems with the system. Figure 4a shows that the feedback system experiences overshoot or undershoot. This is caused by the time occupied by the software program loop. Figure 4a shows that VDAC increases to its maximum value before VOUT reaches the set value. When VOUT finally reaches the set value, VDAC must decrease, and reducing the DAC output voltage takes time, resulting in VOUT undershoot. Ideally, VDAC should change at the same rate as VOUT, but this balance cannot be achieved until the system load reaches a certain level. The system requires 100μs to adjust for large output voltage changes because the software needs to change VDAC bit by bit after ADC sampling. To change VOUT from 5V to 1.25V, the MCU must increase the voltage of the 12-bit DAC 4,095 times while sampling VOUT 4,095 times, each ADC sampling consuming sampling and conversion time.