Preface: After rapid development in recent years, embedded systems have become one of the fastest-growing branches of the electronics and information industry. With the widespread application of emerging products such as mobile phones, PDAs, GPS devices, and set-top boxes, the embedded systems market is growing at a rate of 30% annually (IDC forecast), and embedded system design has become an increasingly important topic for software and hardware engineers. In embedded system design, low-power design is a problem that many designers must face. This is because embedded systems are widely used in portable and highly mobile products, which often rely on batteries rather than a constant power supply. Therefore, designers must consider every detail to reduce power consumption and extend battery life as much as possible. In fact, considering low-power design from a holistic perspective has become an increasingly urgent issue. So, from what aspects should we consider low-power design? The author believes that the following aspects should be considered comprehensively: processor selection, interface driver circuit design, dynamic power management, and power supply circuit selection . We will discuss these separately below: I. Processor Selection Our selection of an embedded system often begins with its CPU and operating system (OS). Once these two are selected, the overall system framework is determined. When choosing a CPU, we generally pay more attention to its performance (such as clock frequency) and the number of interfaces and functions it provides, often neglecting its power consumption characteristics. However, since the CPU is the main source of power consumption in an embedded system—for handheld devices, it accounts for almost half of the total system power consumption except for the display (depending on the specific system)—choosing a suitable CPU has a significant impact on the final system power consumption. Generally, we compare and select based on CPU performance and power consumption. This is usually measured by the energy consumed per million instructions executed, i.e., Watt/MIPS. However, this is only a reference indicator. In reality, the architectures of different CPUs vary greatly, and the methods for measuring performance are also different. Therefore, we should further analyze some details. We divide CPU power consumption into two main parts: core power consumption (PCORE) and external interface controller power consumption (PI/O). The total power is equal to the sum of the two, i.e., P = PCORE + PI/O. For PCORE, the key factors are its supply voltage and clock frequency; for PI/O, in addition to paying attention to the power consumption of each dedicated I/O controller, the address and data bus widths must also be considered. We will discuss each separately below: 1. CPU Supply Voltage and Clock Frequency We know that in digital integrated circuit design, the static power consumption of CMOS circuits is very low and can be basically ignored compared to their dynamic power consumption, so we will not consider it for now. The formula for calculating its dynamic power consumption is: Pd = CTV²f Where, Pd — dynamic power consumption of the CMOS chip CT — load capacitance of the CMOS chip V — operating voltage of the CMOS chip f — operating frequency of the CMOS chip From the above formula, we can see that the power consumption in a CMOS circuit is linearly related to the switching frequency of the circuit and quadraticly related to the supply voltage. For a CPU, the higher the Vcore voltage and the faster the clock frequency, the greater the power consumption. Therefore, under the premise of normal function, choosing a CPU that operates at the lowest possible voltage can achieve better results in terms of overall power consumption. For a selected CPU, reducing the supply voltage and operating frequency is also a feasible way to save power. 2. Bus Width We often fall into a misconception that the wider the CPU external bus, the better. If we only consider data transfer speed, this view may be correct, but in a design that is highly sensitive to power consumption, this view is not necessarily correct. Using the formula Pd=CTV2f, each line (address and other data lines) will face such power consumption. Obviously, the wider the bus width, the greater the power consumption. The capacitive load of each line is different, but it is generally between 4 and 12pF. Let's look at the following example: a 1Mbit Flash is connected to the CPU through an 8-bit and a 16-bit bus, the bus frequency is 4MHz, and the bus voltage is 3.3V. We can obtain the following results: [IMG=Bus Width Result]/uploadpic/THESIS/2007/12/2007121210535581108V.jpg[/IMG] As can be seen above, there is a 3.7mW power consumption difference between using a 16-bit bus and an 8-bit bus. Of course, in situations requiring frequent and large-scale data access, using an 8-bit bus may not be economical because it increases read/write cycles. Furthermore, from the example above, we can also see that if the CPU uses built-in Flash memory, system power consumption can be significantly reduced. II. Low-Power Design of Interface Driver Circuits Low-power design of interface circuits is often an easily overlooked aspect. In this aspect, in addition to considering the selection of peripheral chips with low quiescent current, we should also consider the following factors: Selection of pull-up/pull-down resistors; Necessity of buffer for handling floating pins; We often arbitrarily determine a pull-up resistor value without careful calculation. Let's do a simple calculation. If we use a 4.7KΩ pull-up resistor in a 3.3V system, the current consumption per pin will be 0.7mA when the output is low. If there are 10 such signal pins, a total of 7mA of current will be consumed. Therefore, we should choose the largest possible resistor value while ensuring normal driving of the subsequent stage (i.e., considering the IC's VIH or VIL). Many current application designs use pull-up resistor values ​​as high as several hundred KΩ. Additionally, when a signal is low most of the time, we can consider using a pull-down resistor to save power. Floating pins of CMOS devices should also be given attention. Because the input impedance of a floating CMOS input is extremely high, it is very likely to induce some charge, causing the device to be damaged by high voltage. It can also cause random changes in the input signal level, leading to the CPU being constantly woken up from sleep mode, thus preventing it from entering sleep mode or causing other inexplicable malfunctions. Therefore, the correct method is to connect unused inputs to VCC or ground. Buffers have many functions, such as level conversion, increasing drive capability, and controlling the direction of data transmission. However, if we add a buffer solely based on drive capability, we should be cautious, as overdriving will lead to more wasted energy. Therefore, we should carefully check whether the chip's maximum output current IOH and IOL are sufficient to drive the next-level IC. If we can avoid using a buffer by selecting appropriate front-end and back-end chips, it will be a significant energy saving. III. Dynamic Power Management (DPM) Dynamic power management refers to saving power by dynamically controlling the system clock or voltage during system operation. This dynamic control is closely related to the system's operating state and is often implemented through software. 1. Selecting Different Operating Modes As mentioned earlier, the system clock has a very significant impact on power consumption. Therefore, in addition to focusing on meeting performance requirements, we must also consider how to dynamically set the clock to achieve maximum power saving. Various frequencies inside the CPU are generated by multiplying the external crystal oscillator frequency through an internal phase-locked loop (PLL). Therefore, whether various operating frequencies can be set through internal registers becomes a key factor in controlling power consumption. Many CPUs now offer multiple operating modes, which can be used to save power. Taking the SAMSUNG S3C2410X (32-bit ARM 920T core) as an example, it provides four operating modes: Normal Mode, Idle Mode, Hibernation Mode, and Power Off Mode. The power consumption of each mode is as follows: [IMG=Power Consumption of Mode]/uploadpic/THESIS/2007/12/2007121210540168737Z.jpg[/IMG] As shown in the image, the CPU consumes significantly more power when running at full speed than when idle or hibernating. The principle of power saving is to ensure that the normal operating mode consumes far less time than the idle or hibernation modes. In devices like PDAs, the system runs at full speed far less often than it is idle. Therefore, we can configure the CPU to operate in an idle state as much as possible, then wake it up via an interrupt to return to normal operating mode, process relevant events, and then re-enter idle mode. 2. Disable Unnecessary Peripheral Controllers Generally, CPUs provide various interface controllers, such as I2C, I2S, LCD, Flash, Timer, UART, SPI, USB, etc. However, not all of these controllers are typically used in a design, so we often leave them in various states without paying attention. However, when you want to save power as much as possible, you must pay attention to their states, because even if they are not in operation, they will still consume current if they are not turned off. Taking the S3C2410X as an example: [IMG=S3C2410X Interface Controller]/uploadpic/THESIS/2007/12/2007121210540698115A.jpg[/IMG] As we can see from the table above, by setting registers, we can selectively disable unnecessary functional modules to save power. For example, in our actual application, ADC, I2C, I2S, and SPI are not used. By setting the CLKCON register, we can save 2mA of current. Of course, some peripheral controllers that are still needed can be dynamically turned off to further save energy. For example, in idle mode, when the CPU core stops running, we can further turn off other peripheral controllers, such as USB, SDI, and FLASH, as long as the I/O controller that wakes up the CPU is working properly. If the CPU is woken up via UART, the UART controller cannot be turned off. After the CPU is woken up, the USB, SDI, and Flash controllers are then turned back on. The above two methods are just the simplest implementations of dynamic power management. One method saves energy by changing the system clock frequency, and the other by controlling the switching on and off of peripheral controllers. Recent research has focused on simultaneously dynamically changing the processor's voltage and frequency to further save power, such as the research on dynamic power management for embedded systems conducted by IBM and MontaVista. This is a more complex and systematic project, involving aspects from hardware to the operating system and application layers. IV. Power Supply Circuit In digital circuit design, engineers often prefer the simplest approach to power supply design. However, when power consumption requirements are stringent, we must carefully consider the voltage conversion structure to use before making a decision. Generally speaking, we have the following methods for voltage conversion: Linear Regulator, DC to DC, and LDO (Low Drop-Out). LDO is essentially a type of linear regulator, mainly used in applications with small voltage drops. Therefore, we will discuss them together as linear regulators. The characteristics of linear regulators are simple circuit structure, fewer required components, and a large input-output voltage drop. However, their fatal weakness is low efficiency and high power consumption. Their efficiency η depends entirely on the output voltage. The following figure is a curve showing the output current of the LM7805 linear regulator relative to the voltage drop. [IMG=LM7805 output current relative to voltage drop curve]/uploadpic/THESIS/2007/12/20071212105421603223.JPG[/IMG] As can be seen from the figure, the larger the voltage drop, the smaller the maximum output current that can be provided. Assuming an LM7805 is used, with an input of 12V, an output voltage of 5V, a voltage drop of 7V, and an output current of 1A, we can calculate the power consumed by the linear regulator as P = ΔV * IOUT = 7 * 1 = 7W, and the efficiency is only η = 5 × 1 / (5 * 1 + 7 * 1) = 41.7%. From this result, we can see that a large portion of the power is consumed by the IC itself. DC-to-DC circuits are characterized by high efficiency and flexible step-up/step-down conversion, but their disadvantages include relatively complex circuitry and greater interference. Commonly used circuits include Boost and Buck converters; the former is used for step-up, and the latter for step-down. A schematic diagram is shown below: [IMG=Schematic Diagram]/uploadpic/THESIS/2007/12/2007121210542629703L.jpg[/IMG] The core of these two circuits is to control the energy conversion between the inductor and capacitor through the switching of the MOSFET. Adjusting the duty cycle of the MOSFET gate pulse signal can control the MOSFET's on/off state, thereby changing the output voltage. The following diagram shows a DC-DC converter circuit that transforms 12V to 5V. The control IC used is the National Semiconductor (NS) LM2596, which actually employs a Buck circuit. The MOSFETs and related control circuitry are located internally within the chip. The conversion efficiency diagram is shown below: [IMG=Conversion Efficiency Diagram]/uploadpic/THESIS/2007/12/2007121211090869197J.jpg[/IMG] As can be seen from the conversion efficiency diagram, when the input is 12V and the output is 5V, the conversion efficiency is approximately 82%, twice that of a linear regulator. The LM2596 has a fixed switching frequency of 130kHz. If we increase the switching frequency of the device, such as using NS's LM2676 (260kHz switching frequency), the efficiency can reach over 88% under the same application conditions. From the above discussion, we can see that using DC-DC voltage conversion circuits under appropriate conditions can effectively save energy and reduce overall power consumption.