In remote measurement and control systems, embedded systems have developed rapidly due to their superior stability and real-time performance compared to traditional platforms. This paper proposes a novel embedded system design method using a DSP chip and VxWorks as the operating system. 1. Working Principle of the Test System The main task of the test system is to process images captured by a camera and converted from digital images using a DSP chip. The entire system consists of a video decoder, a DSP, and a dedicated PLC bus chip. The system exchanges data with the communication platform via the PLC bus and performs detection and control via the network. 2. Key Design and Component Selection The key to this system design is the design of the video processing card. General video detection cards have limited functionality and cannot meet the requirements of this project. Therefore, the author designed a custom video detection card. 2.1 Functional Characteristics of TMS320C32 The DSP chip used in this test system is the TI TMS320C3x series product. This device operates at a frequency of 40MHz and uses a Harvard bus architecture. It also features a unique instruction set and hardware multiply-accumulate operations; it includes 256k×32-bit FLASH, 2K×8-bit NVRAM, and 256K×32-bit SRAM. This chip is a simplified version of the TMS320C30, containing the TMS320C30's CPU core. The main functions of the TMS320C32 are as follows: It features program boot functionality; serial interface transmission and memory support for 8, 16, and 32-bit data; it can generate edge interrupts and level interrupts; the interrupt vector table address can be set by the user; it has both no-wait and low-power power management modes; it has two DMA channels; its powerful external memory interface can meet the requirements of 8-bit data for video decoding interfaces and also realize high-speed data transmission of 32-bit data for PLC interfaces; flexible program loading allows for in-system programming; Generally, the hardware connection between the S5933 and the DSP utilizes the DSP's read/write signal R/W, address strobe control signal IOSTRB, external device ready signal RDY, and some address signals, as well as the S5933's FIFO status signal WRFULL, to perform simple timing and logic combinations, thereby generating read/write control signals for the S5933's external bus interface. 2.2 Selection of Other Components The CPLD chip used in this system is the ALTERA EPM9320RC208. The two frame memories, A and B, utilize two CY7C1049 chips manufactured by Cypress. These chips have a capacity of 512k×8bit and an access time of no more than 15ns, meeting the requirements for real-time image acquisition. A ping-pong switch control module within the CPLD automatically switches between the two inter-frame read/write channels. All control signal interface logic and timing conversions between the DSP and SAA7113 are handled by the CPLD and are programmable, thus improving the system's flexibility and reliability. The SAA7113 performs A/D conversion of analog images. The control logic of the hardware interface between the DSP and SAA7113 includes two sub-modules: a frame image writing controller and a ping-pong switch; both functions can be performed by a single CPLD. In video card design, the power supply module is also crucial, directly affecting the final implementation and stable operation of the video card. This monitoring system uses the TI TPS3307-33D as the power detection IC. The effective power reset voltage of this device is defined as VDD=1.1V. The TPS3307-33D can simultaneously monitor two independent voltages and control another voltage, which can be independently adjusted and internally connected to the reset logic circuit. 3. Embedded System Design of the Communication Platform The software system of this design consists of two parts: low-level software and system software. The low-level software mainly includes DSP image processing algorithms and startup programs. These programs can be written in C language and optimized using assembly language in the CCS environment. CCS is a DSP software runtime environment released by TI. Regarding the system software, the image processing system based on the PLC bus faces many challenges, the most difficult of which is the PLC driver problem. 3.1 System Software Design The system software can use an embedded design method with VxWorks as the operating system. The integrated environment of the VxWorks operating system is called Tornado. The Tornado integrated environment is a highly efficient and clear graphical real-time application development platform, which includes a complete set of development and debugging tools for embedded systems. The advantages of VxWorks are as follows: (1) It has good scalability; (2) It supports dynamic linking and dynamic downloading of applications; (3) It has good compatibility; (4) It has high reliability and stability; (5) It has good real-time performance; VxWorks' multi-tasking mechanism adopts priority preemption and round-robin scheduling mechanism for task control, thereby fully guaranteeing real-time performance, and can meet stronger real-time requirements with the same hardware configuration, so as to leave more room for application development. PLC devices have three physical storage spaces: configuration space, memory space and I/O space. The configuration space is a continuous space with a length of 256 bytes. The space definition is shown in Figure 4. In the configuration space, the read-only space includes device identifier, supplier code, modification version, classification code and header type. The supplier code is used to identify the code of the device supplier; the device identifier is used to identify a specific device; the modification version identifies the version number of the device; the classification code is used to identify the type of device; and the header type is used to identify the header type and whether it is a multi-functional device. Except for the supplier code, the values ​​of other fields can be assigned by the supplier. The most important function of the base address register is to allocate the system address space of the PLC device. In the base address register, the least significant bit (Bit I/O) is used to identify whether it is memory space or I/O address space. When the base address register is mapped to memory space, Bit 0 is "0", and when it is mapped to I/O address space, Bit 0 is "1". When driving a PLC device, the first step is to find the PLC device. Embedded operating systems generally provide corresponding API functions for this purpose. In the VxWorks operating system, the functions PLCFIndDevICe(PLC_VENDOR_ID) PLC_DEVICE index &PLCBus &PLCDEVICE, &PLCFunc_ can find the nth (index+1)th device with vendor code PLC_VENDOR_ID and device identifier PLC_DEVICE, and return the bus number, device number, and function number, which are then stored in &PLCBus, &PLCDEVICE, and &PLC-Func respectively. The next step is to configure the PLC device. The configuration space of a PLC device can be accessed through API functions provided by the operating system, thereby configuring the PLC device's base address register, interrupts, and ROM base address register, ultimately obtaining the mapping between the PLC memory space and I/O address space, as well as the device interrupt number. In the VxWorks operating system, API functions for accessing the PLC device configuration space include `PLC ConfigOutLong` and `PLC ConfigOutLong`, which can respectively perform read and write operations on the PLC device's configuration space. Then, based on the PLC device's configuration parameters, initialization programs, interrupt service routines, and programs for accessing the PLC device's memory space are written. 3.2 Remote Control and Communication Link Since the PPP protocol based on serial ports is now accepted by various ISPs, and the VxWorks system also supports the PPP protocol, a physical connection with the ISP can be established via a modem under VxWorks, and then the PPP data link settings for the device can be completed, enabling remote control via the Internet.